公开(公告)号：AU6131590A

公开(公告)日：1991-03-21

申请号：AU6131590

申请日：1990-08-24

Applicant: IBM

Inventor： SCHEITTLER HELMUT ,  SCHULZ UWE ,  ZUHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538 ,  H01L27/06

Abstract: A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.

公开(公告)号：AU630225B2

公开(公告)日：1992-10-22

申请号：AU6131590

申请日：1990-08-24

Applicant: IBM

Inventor： SCHEITTLER HELMUT ,  SCHULZ UWE ,  ZUHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538 ,  H01L27/06

Abstract: A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.