公开(公告)号：DE68926886T2

公开(公告)日：1997-02-06

申请号：DE68926886

申请日：1989-09-15

Applicant: IBM

Inventor： SCHETTLER HELMUT DIPL ING ,  SCHULZ UWE ,  ZUEHLKE RAINER DR ING

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538

Abstract: A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.

公开(公告)号：CA2024848A1

公开(公告)日：1991-03-20

申请号：CA2024848

申请日：1990-09-07

Applicant: IBM

Inventor： SCHETTLER HELMUT ,  SCHULZ UWE ,  ZUEHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538 ,  H01L23/12

Abstract: DESIGN SYSTEM FOR VLSI CHIPS ARRANGED ON A CARRIER AND MODULE THUS DESIGNED A system design for VLSI chips arranged on a carrier and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. A carrier that is included in the design from the beginning, preferably a thin film passive silicon carrier, is used.

公开(公告)号：SG46176A1

公开(公告)日：1998-02-20

申请号：SG1996000136

申请日：1989-09-15

Applicant: IBM

Inventor： SCHETTLER HELMUT ,  SCHULZ UWE ,  ZUEHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538

Abstract: A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.

公开(公告)号：HK203396A

公开(公告)日：1996-11-15

申请号：HK203396

申请日：1996-11-07

Applicant: IBM

Inventor： SCHETTLER HELMUT DIPL-ING ,  SCHULZ UWE ,  ZUEHLKE RAINER DR-ING

IPC: H01L23/14 ,  H01L23/538

公开(公告)号：CA1275508C

公开(公告)日：1990-10-23

申请号：CA554556

申请日：1987-12-16

Applicant: IBM

Inventor： KLEIN KLAUS ,  POLLMANN KURT ,  SCHETTLER HELMUT ,  SCHULZ UWE ,  WAGNER OTTO M ,  ZUEHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L21/822 ,  H01L27/04 ,  G06F15/60

Abstract: HIERARCHICAL TOP-DOWN METHOD FOR PHYSICAL VLSI-CHIP DESIGN For the physical design of a VLSI chip a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology the circuitry to be contained on the chip is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus the different partitions are designed in parallel. A floor plan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip needs no extra space for global wiring and the partitions are immediately attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.

公开(公告)号：BR8706324A

公开(公告)日：1988-07-19

申请号：BR8706324

申请日：1987-11-24

Applicant: IBM

Inventor： KLEIN KLAUS ,  POLLMANN KURT ,  SCHETTLER HELMUT ,  SCHULZ UWE ,  WAGNER OTTO M ,  ZUEHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L21/822 ,  H01L27/04 ,  H01L21/92

Abstract: For the physical design of a VLSI chip a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology the circuitry to be contained on the chip is logically devided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus the different partitions are designed in parallel. A floorplan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip need no extra space for global wiring and the partitions are immediataly attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.

公开(公告)号：MY130151A

公开(公告)日：2007-06-29

申请号：MYPI9001368

申请日：1990-08-15

Applicant: IBM

Inventor： SCHETTLER HELMUT ,  SCHULZ UWE ,  ZUHLKE RAINER

IPC: H01L23/538 ,  H01L23/14

Abstract: A SYSTEM DESIGN FOR VLSI CHIPS ARRANGED ON A CARRIER AND THE MODULE THUS DESIGNED IS DESCRIBED. IN A TOP-DOWN DESIGN SYSTEM SYNOPTICALLY AND SIMULTANEOUSLY AN ELECTRICAL CIRCUITRY IS OPTIMIZED BY DESIGNING SYNOPTICALLY THE CHIPS AND THE CHIP CARRIER. THE OVERALL LOGIC IS DIVIDED IN PARTITIONS WHICH FIT ON CHIPS. A CHIP PLACEMENT ON THE CARRIER IS PERFORMED CONSIDERING MINIMUM OVERALL CONNECTION LENGTH AND PROVIDING PREFERABLY PARALLEL CONNECTION. INPUT/OUTPUT CONTACTS ARE ASSIGNED ON CHIPS VIS-A-VIS EACH OTHER WHEN THEY CORRESPOND. THEY ARE CONNECTED BY PARALLEL LINES. THE DESIGN OF THE SEVERAL CHIPS IS DONE FROM OUTSIDE TO INSIDE, STARTING WITH THE ASSIGNED I/O CONTACTS. OVERALL, IN COMBINING OPTIMUM OVERALL DESIGN AND OPTIMUM CHIP DESIGN, A SEMICONDUCTOR THIN FILM SILICON MULTICHIP MODULE OF HIGH YIELD AND PERFORMANCE IS PROVIDED. AS CARRIER THAT IS INCLUDED IN THE DESIGN FROM THE BEGINNING, PREFERABLY A THIN FILM PASSIVE SILICON CARRIER IS USED.(FIG 6)

公开(公告)号：AU6131590A

公开(公告)日：1991-03-21

申请号：AU6131590

申请日：1990-08-24

Applicant: IBM

Inventor： SCHEITTLER HELMUT ,  SCHULZ UWE ,  ZUHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538 ,  H01L27/06

Abstract: A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.

公开(公告)号：DE68926886D1

公开(公告)日：1996-08-29

申请号：DE68926886

申请日：1989-09-15

Applicant: IBM

Inventor： SCHETTLER HELMUT DIPL ING ,  SCHULZ UWE ,  ZUEHLKE RAINER DR ING

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538

Abstract: A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.

公开(公告)号：AU630225B2

公开(公告)日：1992-10-22

申请号：AU6131590

申请日：1990-08-24

Applicant: IBM

Inventor： SCHEITTLER HELMUT ,  SCHULZ UWE ,  ZUHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538 ,  H01L27/06

Abstract: A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.