公开(公告)号：GB2455406A

公开(公告)日：2009-06-10

申请号：GB0821864

申请日：2008-12-01

Applicant: IBM

Inventor： FUCHS THOMAS ,  KOEHLER THOMAS ,  SCHLECHTER SIEGMUND

IPC: G06F12/10 ,  G06F9/38 ,  G06F12/1027

Abstract: A memory attached accelerator has a micro architecture comprising at least one co-processor separated from at least one core processor, wherein the co-processor directly uses the instructions of the core processor and directly accesses a main storage using virtual addresses of the core processor. The co-processor includes a Translation Lookaside Buffer (TLB) that preferably comprises at least one entry in the form of tag information stored in a tag register which assigns a virtual address to an absolute memory address. The TLB is preferably divided into compartments of a specified number of entries, each compartment holding translations for a consecutive set of pages representing a data compression dictionary. The tag information is maintained only for the starting page of the dictionary and is loaded and compared only once per operation. In the case of a TLB hit, the respective absolute address is sent to a dedicated cache for fetching the data.