公开(公告)号：EP1905081A4

公开(公告)日：2012-06-20

申请号：EP06785245

申请日：2006-06-21

Applicant: IBM

Inventor： GREENBERG DAVID R ,  PEKARIK JOHN J ,  SCHOLVIN JORG

IPC: H01L29/41 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2007002158A2

公开(公告)日：2007-01-04

申请号：PCT/US2006024085

申请日：2006-06-21

Applicant: IBM ,  GREENBERG DAVID R ,  PEKARIK JOHN J ,  SCHOLVIN JORG

Inventor： GREENBERG DAVID R ,  PEKARIK JOHN J ,  SCHOLVIN JORG

IPC: H01L23/52

CPC classification number: H01L23/528 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Multilevel metallization layouts for an integrated circuit chip (30) including transistors having first (31 ), second (32) and third (33) elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection (39) for the second contact vertically (32) from the chip (30), overlapping the planes and fingers of the metallization layouts to the first and second elements (31 ) and (32) and forming a pyramid or staircase of multilevel metallization layers (45) and (46) to smooth diagonal current flow.

Abstract translation: 用于集成电路芯片（30）的多层金属化布局包括具有金属化布局连接的第一（31），第二（32）和第三（33）元件的晶体管。 布局通过将来自芯片（30）的垂直（32）的第二触点的连接（39）定位成与金属化布局的平面和手指重叠到第一和第二元件（31）和（ 32）并且形成多层金属化层（45）和（46）的金字塔或楼梯以平滑对角线电流。