公开(公告)号：DE3171882D1

公开(公告)日：1985-09-26

申请号：DE3171882

申请日：1981-03-31

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： GOTZE VOLKMAR ,  SCHUTT DIETER DR

IPC: G06F7/00 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/20 ,  G06F11/26 ,  H03K19/177

Abstract: An apparatus and a method to automatically locate defects and to automatically insert and personalize dummy lines in a PLA having latches controlling the cross points of the AND and OR array. Upon occurrence of an error in the PLA, a check signal is generated which interrupts normal operation of the PLA and which initiates a test procedure. The cross point latches are automatically loaded with test patterns and the output of the PLA is analyzed to locate the defective part, for example, a damaged cross point transistor, short circuited or open line. The dummy lines are repersonalized automatically to replace lines which are defective themselves or which are connected to defective crosspoints.

公开(公告)号：DE3064445D1

公开(公告)日：1983-09-01

申请号：DE3064445

申请日：1980-11-14

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： GOTZE VOLKMAR ,  SCHUTT DIETER DR

IPC: G06F11/00 ,  G06F11/08 ,  H03K19/02 ,  H03K19/177 ,  G06F11/12

Abstract: Error detection and correction apparatus for a programmable logic array (PLA) having AND and OR logic combinations merged therein is disclosed. The output lines from the AND and OR logic elements are coupled in such a manner that their functions form complete groups containing, if possible, all minterms. Missing minterms are added, as necessary, by special output lines or logic elements provided for that purpose to complete a group. If a minterm occurs on two or more function lines, the corresponding minterm is entered as a correction term into an error detection logic means, one of which is associated with each group of logic output lines. The error detection logic means are also utilized to test whether one, and only one, of the output lines in a grouping of function lines has a binary 1 value. Error correction signals are generated by mixed group error detection means, the inputs of which are connected to a function line of another function group. If a single error is detected, the error detection logic means for the function line groups indicate which group includes the erroneous function line. The mixed group error detection means similarly indicate, if appropriate, which of function lines of the mixed group is erroneous.

公开(公告)号：DE3070320D1

公开(公告)日：1985-04-25

申请号：DE3070320

申请日：1980-09-27

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： HEINRICH HANS JOACHIM ,  SCHUTT DIETER DR

IPC: G06F9/48 ,  G06F15/16 ,  G06F15/177 ,  G06F9/46

Abstract: Interrupt requests of different priorities, presented by various interrupt sources (0 to 3), are transferred through control ST, in an associative storage and selection process, into preprocessing elements PE0 and PE1. These elements are variably assigned by controls ST to receive and preprocess requests of associated priority. The preprocessing generates a starting address of a program routine for servicing the respective request. This address is transferred to a common processor which executes the routine. The preprocessing elements can be structured to rapidly generate a succession of different starting addresses relative to several interrupt requests having the priority assigned to that element.

公开(公告)号：DE3167134D1

公开(公告)日：1984-12-20

申请号：DE3167134

申请日：1981-02-25

Applicant: IBM

Inventor： SCHUTT DIETER DR ,  SCHWENGLER MANFRED DR ,  ULLAND HARTMUT ,  WEIS HELMUT

IPC: G06F3/153 ,  G06F12/02 ,  G06F13/00 ,  G09G1/16 ,  G09G5/00 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395

Abstract: A device for storing and displaying graphic information having a storage unit for storing both blocks and rows of data and retrieving rows of data. The storage unit consists of two storage segments, with eight storage modules each, which can operate in an interleaved mode. This permits two-dimensional addressing which consists of distributing the individual elements of a data block over the various separately addressable modules of the storage unit so that no one module contains more than one element of the data block, and that all elements of the data block can be read out in one cycle through simultaneous access of all of the storage modules.