公开(公告)号：US3675218A

公开(公告)日：1972-07-04

申请号：US3675218D

申请日：1970-01-15

Applicant: IBM

Inventor： SECHLER ROBERT F

IPC: G11C8/16 ,  G11C11/411 ,  H03K3/2885 ,  G11C11/40

CPC classification number: H03K3/2885 ,  G11C8/16 ,  G11C11/4113

Abstract: A memory array is formed of a plurality of memory cells arranged in a matrix and providing for the simultaneous writing of information into one portion of the array while accomplishing the retrieval of information from another portion of the array. Each cell of the array utilizes cross-coupled flip flops as the storage circuit and includes control circuitry for reading from the cell and independent control circuitry for writing into the cell. Each cell of the array is further expandable by adding appropriate reading and/or writing control circuits for providing multiple data in and/or data out bussing.

Abstract translation: 存储器阵列由布置在矩阵中的多个存储单元形成，并且提供将信息同时写入阵列的一部分，同时完成从阵列的另一部分检索信息。 阵列的每个单元都使用交叉耦合触发器作为存储电路，并且包括用于从单元读取的控制电路和用于写入单元的独立控制电路。 通过添加适当的读取和/或写入控制电路来对数组的每个单元进一步扩展，以便在和/或数据输出中提供多个数据。

公开(公告)号：CA1009315A

公开(公告)日：1977-04-26

申请号：CA171603

申请日：1973-05-15

Applicant: IBM

Inventor： JORDAN PAUL V ,  SECHLER ROBERT F

IPC: H04L25/02 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/088