公开(公告)号：US3699362A

公开(公告)日：1972-10-17

申请号：US3699362D

申请日：1971-05-27

Applicant: IBM

Inventor： JORDAN PAUL V

IPC: H01L27/02 ,  H03K17/16 ,  H03K19/088 ,  H03K19/34

CPC classification number: H01L27/0248 ,  H03K17/16 ,  H03K19/088

Abstract: A transistor-transistor logic circuit employing a Schottky barrier diode connected across the output of the multi-emitter input transistor and the reference potential to suppress transient overshoot by controlling the voltage at the collector of the input transistor of the TTL circuit.

Abstract translation: 采用在多发射极输入晶体管的输出端连接的肖特基势垒二极管和参考电位的晶体管晶体管逻辑电路，通过控制TTL电路的输入晶体管的集电极处的电压来抑制瞬态过冲。

公开(公告)号：US3678475A

公开(公告)日：1972-07-18

申请号：US3678475D

申请日：1971-02-01

Applicant: IBM

Inventor： JORDAN PAUL V ,  PALMIERI JOHN A ,  WADE WILLIAM T

IPC: G11C17/08 ,  G11C11/40 ,  G11C17/00

CPC classification number: G11C17/08

Abstract: A method and apparatus for storing in a read only memory a matrix having one or more rows each with a majority of '''' 1'''' bits. There is formed the complement of each of those rows having a majority of '''' 1'''' bits to form a new matrix wherein no row has a majority of '''' 1'''' bits. The new matrix is stored in a read only memory. Upon reading out one or more rows of the matrix the bits of the complemented rows are reinverted.

Abstract translation: 一种用于在只读存储器中存储具有一行或多行具有多数“1”位的矩阵的方法和装置。 形成具有大多数“1”位的那些行中的每一行的互补以形成其中没有行具有多数“1”位的新矩阵。 新矩阵存储在只读存储器中。 在读取矩阵的一行或多行时，补码行的位被重新转换。

公开(公告)号：CA1009315A

公开(公告)日：1977-04-26

申请号：CA171603

申请日：1973-05-15

Applicant: IBM

Inventor： JORDAN PAUL V ,  SECHLER ROBERT F

IPC: H04L25/02 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/088

公开(公告)号：CA965479A

公开(公告)日：1975-04-01

申请号：CA154488

申请日：1972-10-17

Applicant: IBM

Inventor： JORDAN PAUL V

IPC: G01R31/3185

Abstract: A plurality of sequential logic circuits are connected to a shift register, both located on the same semiconductor chip. Input test data supplied at a chip input pad is routed via parallel paths interconnecting the sequential logic circuits to the shift register for performing combinatorial logic tests. The test responses are accessible to a chip output pad via the shift register. The shift register functions as virtual input/output pads so as to permit combinatorial logic testing on high density sequential logic circuits without increasing the actual input/output pad requirements of the semiconductor chip.