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公开(公告)号：DE3063100D1
公开(公告)日：1983-06-16
申请号：DE3063100
申请日：1980-06-24
Applicant: IBM
Inventor： COCKE JOHN , MALM RICHARD LAVERNE , SHEDLETSKY JOHN JAMES
Abstract: A computer system for simulation of logic operations comprised of an array of specially designed parallel processors (1-31), there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory (202). Logic values simulated by one processor are communicated to other processors by a switching mechanism (33) controlled by a controller (32). If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks (35, 36) for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks (38, 39) are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.
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公开(公告)号：IT1150956B
公开(公告)日：1986-12-17
申请号：IT2260580
申请日：1980-06-06
Applicant: IBM
Inventor： COCKE JOHN , MALM RICHARD LAVERNE , SHEDLETSKY JOHN JAMES
Abstract: A computer system for simulation of logic operations comprised of an array of specially designed parallel processors (1-31), there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory (202). Logic values simulated by one processor are communicated to other processors by a switching mechanism (33) controlled by a controller (32). If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks (35, 36) for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks (38, 39) are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.
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公开(公告)号：IT8022605D0
公开(公告)日：1980-06-06
申请号：IT2260580
申请日：1980-06-06
Applicant: IBM
Inventor： COCKE JOHN , MALM RICHARD LAVERNE , SHEDLETSKY JOHN JAMES
Abstract: A computer system for simulation of logic operations comprised of an array of specially designed parallel processors (1-31), there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory (202). Logic values simulated by one processor are communicated to other processors by a switching mechanism (33) controlled by a controller (32). If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks (35, 36) for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks (38, 39) are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.
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