公开(公告)号：DE3579422D1

公开(公告)日：1990-10-04

申请号：DE3579422

申请日：1985-11-22

Applicant: IBM

Inventor： SHIBATA ICHIROH ,  WATANABE SHINPEI

IPC: G09G5/10 ,  G09G1/16 ,  G09G5/02 ,  G09G5/06 ,  G09G5/30 ,  G09G1/28

Abstract: The display system comprises a color map memory or palette circuit (30) with a plurality of registers (32) for converting a color code to a color video signal and a blinking circuit. The blinking circuit is composed of at least two blink color registers (46,48), a blink code register (50), and a blink control circuit (42). Prior to blinking, a processor loads the address of a palette register retaining a color to be blinked into the blink code register, loads a color video signal (e.g. 6-bit signal) representing the color to be blinked into a selected blink color register, and loads a color video signal representing a different color to be displayed alternately with the color to be blinked into the other blink color register. The control circuit alternately writes the contents of the blink color registers into the palette register specified by the address in the blink code register, in synchronization with a blink clock. Thus, a specified color and a different color are displayed alternately at dot positions of the specified color, to achieve color blinking.