公开(公告)号：JPH02128398A

公开(公告)日：1990-05-16

申请号：JP24089989

申请日：1989-09-19

Applicant: IBM

Inventor： SHIRUBEN RUFUORESUTEIE ,  DOMINIIKU OME

IPC: G11C11/413 ,  G11C8/10 ,  G11C11/415

Abstract: PURPOSE: To increase a speed and to reduce power consumption by constituting the subject circuit with a first stage containing a differential cascode current switch tree and plurality of advance decoder circuits provided with a constant current source and a second stage containing plural final decoder circuits dynamically activated in response to a control signal. CONSTITUTION: The advance decoder circuits PDP, PDQ of the first stage consist of a low power high speed differential cascode current switch tree and the constant current source, and generate advance decoded output signals P1-P8, Q1-Q8 in response to input address signals A1-A8 and inversion signals -A1 to -A8. The final decoder circuits FD1-64 of the second stage consist of an OR gate activated by a switch type current source, and inputs a pair of advance decoded signals to output drive signals X1-X64 of word lines X1-X64 of a memory cell array MA. Since the switch type current source is started by the control signal SWL from a clock generation mechanism CG, the FD circuits compensate power only when the control signal SWL is an active state. Thus, the speed is increased, and the power consumption is reduced.