公开(公告)号：JPH02158998A

公开(公告)日：1990-06-19

申请号：JP27050089

申请日：1989-10-19

Applicant: IBM

Inventor： SHIRUBEEN RUFUORESUTEIE ,  DOMINIIKU OME

IPC: G11C7/06 ,  G11C11/416

Abstract: PURPOSE: To attain operation in a constant state by providing common base amplifier means connected to a reference voltage generator. CONSTITUTION: By selecting proper values of resistors R1-R8 and current sources IB1-IB6, a voltage gain becomes maximum at the time of high-speed operation. The saturation of a first differential amplifier stage of transistors T3, T4 is avoided by adjusting a voltage between both ends of resistors R3, R4 to be less than the saturation. The saturation of a second differential amplifier stage of transistors T5, T6 is prevented by means of a reference voltage generating circuit 13. Dot coupled capacitance received by a first stage is sharply decreased by a second stage or a final stage. The maximum voltage applied on the common base of transistors T9, T10 is VREF, the minimum voltage applied on the collector electrodes when they are turned off is VH-2VBE and thus 0.5VBE is used for preventing the saturation of transistors T9, T10. Consequently, the output swing of the final stage is restricted to a value lower by 2VBE than VH and a high swing signal is supplied to a BICMOS circuit connected to a terminal 18. Thus, the circuit is operated in a constant state.

公开(公告)号：JPH02128398A

公开(公告)日：1990-05-16

申请号：JP24089989

申请日：1989-09-19

Applicant: IBM

Inventor： SHIRUBEN RUFUORESUTEIE ,  DOMINIIKU OME

IPC: G11C11/413 ,  G11C8/10 ,  G11C11/415

Abstract: PURPOSE: To increase a speed and to reduce power consumption by constituting the subject circuit with a first stage containing a differential cascode current switch tree and plurality of advance decoder circuits provided with a constant current source and a second stage containing plural final decoder circuits dynamically activated in response to a control signal. CONSTITUTION: The advance decoder circuits PDP, PDQ of the first stage consist of a low power high speed differential cascode current switch tree and the constant current source, and generate advance decoded output signals P1-P8, Q1-Q8 in response to input address signals A1-A8 and inversion signals -A1 to -A8. The final decoder circuits FD1-64 of the second stage consist of an OR gate activated by a switch type current source, and inputs a pair of advance decoded signals to output drive signals X1-X64 of word lines X1-X64 of a memory cell array MA. Since the switch type current source is started by the control signal SWL from a clock generation mechanism CG, the FD circuits compensate power only when the control signal SWL is an active state. Thus, the speed is increased, and the power consumption is reduced.

公开(公告)号：JPH02268016A

公开(公告)日：1990-11-01

申请号：JP5288890

申请日：1990-03-06

Applicant: IBM

Inventor： JIERAARU BUDON ,  PIEERU MORIE ,  SEIKI OGURA ,  DOMINIIKU OME ,  PASUKARU TANOFU ,  FURANKU WARAARU

IPC: H03K19/086 ,  H03F1/30 ,  H03F3/30 ,  H03K17/56 ,  H03K17/567 ,  H03K17/66 ,  H03K19/01 ,  H03K19/013 ,  H03K19/018 ,  H03K19/08

Abstract: PURPOSE: To quicken the operating speed and to reduce current consumption by providing a voltage converter circuit between NPN and PNP output transistors(TRs), selecting a DC voltage shift to be a shift to warrant both a minimum crossover current and a minimum delay and setting the shift point to be an operating point. CONSTITUTION: Two output bipolar TRs, an upper NPNT 1 and a lower PNPT 2 are connected by a common coupling node N and a 1st power supply voltage VH and a 2nd power supply voltage GND are given to both ends of the TRs T1, T2. The output node N is connected to a terminal 15, at which an output signal VOUT is available and a voltage conversion circuit SA1 is placed between a base and a node of each TR. Then the base node is driven by a logic signal IN 1 fed from a preceding drive circuit and the complementary emitter follower driver is operated at a conduction limit independently of a threshold level of the TRs.