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公开(公告)号:AT387781T
公开(公告)日:2008-03-15
申请号:AT03722876
申请日:2003-05-16
Applicant: IBM
Inventor: PEYRAVIAN MOHAMMAD , RINALDI MARK , SIEGEL MICHAEL , SABHIKHI RAVINDER
IPC: H04L47/724 , H04L12/40
Abstract: A Resource Reservation System includes a Token Generation Unit (TGU) which generates and circulates among nodes of a communications system a Slotted Token (SLT) message having sub-fields to carry identification number for each input port in a node and the resource available for each input port. On receiving the message the Resource Control Unit (RCU) in each node can write port identification number, available resource in appropriate sub-fields of the SLT message, and reserve resources in other nodes by adjusting information in the sub-field associated with the other nodes.
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公开(公告)号:AT384380T
公开(公告)日:2008-02-15
申请号:AT01917224
申请日:2001-03-26
Applicant: IBM
Inventor: BASS BRIAN , CALVIGNAC JEAN , HEDDES MARCO , SIEGEL MICHAEL , VERPLANKEN FABRICE
Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.
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公开(公告)号:AT431028T
公开(公告)日:2009-05-15
申请号:AT00959159
申请日:2000-08-24
Applicant: IBM
Inventor: ALLEN JAMES , BASS BRIAN , CALVIGNAC JEAN , GAUR SANTOSH , HEDDES MARCO , SIEGEL MICHAEL , VERPLANKEN FABRICE
Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
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公开(公告)号:AT435556T
公开(公告)日:2009-07-15
申请号:AT00976194
申请日:2000-11-21
Applicant: IBM
Inventor: AYDEMIR METIN , BASS BRIAN , JEFFRIES CLARK , ROVNER SONIA , SIEGEL MICHAEL , GALLO ANTHONY , GORTI BRAHMANAND , HEDDES MARCO
IPC: H04L47/30
Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.
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公开(公告)号:DE60033529T2
公开(公告)日:2007-11-15
申请号:DE60033529
申请日:2000-08-24
Applicant: IBM
Inventor: BASS BRIAN , CALVIGNAC JEAN , HEDDES MARCO , PATEL PIYUSH , REVILLA JUAN , SIEGEL MICHAEL , VERPLANKEN FABRICE
IPC: G06F15/16 , G06F15/167 , G06F12/00 , G06F12/06 , G06F13/16 , G06F15/177 , H04L12/56 , H04Q11/04
Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.
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