公开(公告)号：JPH11316681A

公开(公告)日：1999-11-16

申请号：JP2418899

申请日：1999-02-01

Applicant: IBM

Inventor： MELTZER DAVID ,  SILBERMAN JOEL ABRAHAM

IPC: G06F12/08 ,  G06F9/32 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To execute loading to an instruction buffer of a super-scalar processor that can issue instructions at random by adding plural slots to the instruction buffer and filling an empty slot of an instruction with instructions given from an instruction cache if a first instruction is not included in a 1st slot of the instruction buffer. SOLUTION: A processor 10 which can issue instructions at random is equipped with an instruction cache 14 having plural cache rows. The cache 14 is connected to an instruction buffer via a multiplexer of an instruction unit 11. Plural slots of the instruction buffer are successively filled with instructions given from the cache 14 under the monitoring of the multiplexer. A slot including a first instruction is identified by a fetch address. If the first instruction is not included in a 1st slot of the instruction buffer, an optional empty slot of the instruction buffer is filled with instructions given from a subsequent cache row of the cache 14.

公开(公告)号：JP2000029694A

公开(公告)日：2000-01-28

申请号：JP7891399

申请日：1999-03-24

Applicant: IBM

Inventor： DHONG SANG H ,  SILBERMAN JOEL ABRAHAM

IPC: G06F9/32 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To shorten an instruction take-out wait time by generating a target address and sequential addresses and the a select signal in parallel. SOLUTION: A decoder 40 determines the target address according to an instruction in a take-out window 38. Further, an adder 48 calculates sequential take-out addresses from the address of the final instruction in an instruction queue 30 and the length of the final instruction. Then priority order logic 42 decides whether or not an unprocessed branch instruction is included in the take-out window 38. When it is decided that no unprocessed branch instruction is included, the priority order logic 41 selects the sequential take-out addresses. A multiplexer 50 selects at least one of decoded input addresses as a memory request address in response to the select signal 52. Then when the solution that the target address is correct is obtained, instructions in a sequential path can be discarded.

公开(公告)号：DE69938911D1

公开(公告)日：2008-07-31

申请号：DE69938911

申请日：1999-02-26

Applicant: IBM

Inventor： DHONG SANG HOO ,  SILBERMAN JOEL ABRAHAM

IPC: G06F9/32 ,  G06F9/38

Abstract: A processor and method of fetching an instruction from a memory are disclosed. According to the method of the present invention, a plurality of target addresses are determined utilizing a plurality of previously fetched instructions, and a sequential address is determined utilizing a last of the plurality of previously fetched instructions. Concurrently with the determination of the target addresses and the sequential address, a select signal specifying one of the plurality of target addresses or the sequential address is generated. The select signal is used to select one of the plurality of target addresses or the sequential address as a memory request address. The memory request address is then transmitted from the processor to the memory so that the memory will supply at least one instruction to the processor. By generating the target addresses and sequential address concurrently with the generation of the selection signal, instruction fetch latency is reduced.