公开(公告)号：DE3484286D1

公开(公告)日：1991-04-25

申请号：DE3484286

申请日：1984-06-08

Applicant: IBM

Inventor： ANDERSEN JOHN E ,  MESSINA BENEDICTO U ,  PETROSKY JOSEPH A ,  SILKMAN WILLIAM D

IPC: G06F12/00 ,  G06F7/02 ,  G06F12/02 ,  G06F12/08 ,  G06F17/30 ,  G06F15/40

Abstract: A directory memory having simultaneous writing and bypass capabilities. A data output bit (DB n ) from a respective memory cell of a memory array is applied to a control input of a first differential amplifier (63, 66), while comparison input data is applied to inputs of a second differential amplifier (64, 65). The outputs of corresponding transistors of the two differential amplifiers are connected together. Current switch transistors (77, 78), operated in response to a bypass select signal, supply current only to one or the other of the two differential amplifiers. The differential output signal produced across the commonly connected outputs of the two differential amplifier circuits is buffered and amplified with a push-pull output circuit (62, 87).

公开(公告)号：CA1143860A

公开(公告)日：1983-03-29

申请号：CA360343

申请日：1980-09-16

Applicant: IBM

Inventor： MESSINA BENEDICTO U ,  SILKMAN WILLIAM D

IPC: G06F12/04 ,  G06F12/08 ,  G06F13/00

Abstract: A cache organization that enables many cache functions to overlap without extending line fetch or line castout time and without requiring a cache technology faster than the main storage transfer rate. Main storage has a data bus-out and a data bus-in, each transferring a double word (DW) in one cycle. Both buses may transfer respective DWs in opposite directions in the same cycle. The cache has a quadword (QW) write register and a QW read register, a QW being two SWs on a QW address boundary. During a line fetch (LF) of 16 DWs, either the first pair of DWs, or the first DW of the LF is loaded into the QW write register, depending on whether the first DW is on a QW address boundary or not, i.e., whether the fetch request address bit 28 is even or odd, respectively. Thereafter during the LF, the even and odd DWs are formed into QWs as received from the bus-out, and the QWs are written into the cache on alternate cycles, wherein no QW cache access occurs on the other alternate cycles for the LF. Either 8 or 9 QWs occur for a LF depending on the first DW boundary alignment. For a LF with 9 QWs, a write inhibit is needed for a non-data odd DW position in the last QW to avoid destroying the first DW written in the cache. If a line castout (CO) is required from the same or a different location in the cache, the CO can proceed during the alternate non-write cycles of any LF. Any cache bypass to the processor during the LF can overlap the LF and CO. Any alternate cycles during any LF, which are not used for a CO or LF bypass, are available for processor request accesses of the cache for either DWs or QWs. PO9-79-006