公开(公告)号：DE3380644D1

公开(公告)日：1989-11-02

申请号：DE3380644

申请日：1983-05-19

Applicant: IBM

Inventor： SINGH SHANKER ,  SINGH VIJENDRA PAL

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/16 ,  G11C29/00 ,  G06F11/00

公开(公告)号：DE3481350D1

公开(公告)日：1990-03-15

申请号：DE3481350

申请日：1984-08-17

Applicant: IBM

Inventor： SHAH SIDDHARTH ROMESHCHANDRA ,  SINGH SHANKER ,  SINGH VIJENDRA PAL

IPC: G06F12/16 ,  G11C29/00 ,  G06F11/00 ,  G06F11/20

Abstract: In a reconfigurable memory a spare chip (40) is substituted for a faulty chip when an uncorrectable error condition results from an alignment of two errors in bit positions accessed through the same chip row decoder (12) while an address bit permutation apparatus (30, 32) is used to misalign faulty bits when they occur in bit positions accessed through different decoders.