公开(公告)号：DE3484542D1

公开(公告)日：1991-06-13

申请号：DE3484542

申请日：1984-03-09

Applicant: IBM

Inventor： SINGH SHANKER ,  SINGH VINJENDRA P

IPC: G06F12/16 ,  G06F11/00 ,  G06F12/00

Abstract: This permutation circuit can be considered to be a multibit adder without a carry. In one embodiment it takes the form of m address bits being fed to m+y 2-way exclusive OR gates (12) with m+y permutation bits to generate m+y input bits accessing a decoder (10) with 2 m output positions. In another embodimentthe decoder takes the form of an m-bit adder (14) which adds m address bits to m permutation bits to generate an m-bit actual address. Multiple decoders of both types may be joinedtogether in various combinationsto generate higher order addresses. Also, k full-adders of less than m bits can be used in similar fashion as m+y Exor gates to provide shift rotate capability within a desired block of 2 Y rows.