公开(公告)号：WO2004099997A9

公开(公告)日：2005-10-27

申请号：PCT/GB2004001971

申请日：2004-05-06

Applicant: IBM ,  IBM UK ,  SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F9/3824 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109

Abstract: Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.

Abstract translation: 所选存储单元（如存储区域或存储区域）无效。 通过设置位于与要被无效的存储单元相对应的数据结构条目中的无效指示符来促进无效。 此外，清除与无效存储单元或其他所选存储单元相关联的缓冲区条目。 提供了执行无效和/或清除的指令。 此外，与特定地址空间相关联的缓冲区条目将被清除，无任何无效。 这也由指令执行。 该指令可以以软件，硬件，固件或其某种组合来实现，或者可以被仿真。

公开(公告)号：DE112004000464T5

公开(公告)日：2006-06-01

申请号：DE112004000464

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

公开(公告)号：GB2413876A

公开(公告)日：2005-11-09

申请号：GB0516192

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

Abstract: Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.

公开(公告)号：DK1588267T3

公开(公告)日：2008-05-13

申请号：DK04731399

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

公开(公告)号：ES2297417T3

公开(公告)日：2008-05-01

申请号：ES04731399

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

Abstract: Un método para borrar memorias intermedias de traducción de direcciones e invalidar una gama de elementos de una tabla de traducción de direcciones de almacenamiento asociadas en un sistema informático, comprendiendo el sistema informático una o más unidades centrales de proceso en comunicación con un almacenamiento principal, teniendo las unidades centrales de proceso unas memorias intermedias de traducción de direcciones, teniendo además la memoria intermedia de traducción de direcciones elementos de memoria intermedia de traducción de direcciones que mantienen la información de traducción de direcciones, teniendo el sistema informático tablas de páginas y otras tablas de traducción de direcciones para traducir las direcciones del almacenamiento principal virtual de una unidad central de proceso de una o más unidades de proceso, en direcciones del almacenamiento principal del sistema informático, comprendiendo las tablas de traducción de direcciones cualquiera de los siguientes: una o mástablas de segmentos, una o más tablas de segmentos y una o más tablas de la primera región, una o más tablas de segmentos y una o más tablas de la primera región y una o más tablas de la segunda región o una o más tablas de segmentos y una o más tablas de la primera región y una o más tablas de la segunda región y una o más tablas de la tercera región, donde un elemento de una tabla de segmentos comprende un origen de la tabla de páginas; estando caracterizado el método porque comprende los pasos de: extraer una instrucción multifunción (600) de ordenador de un Elemento de Tabla de Traducción Dinámica de Direcciones de Invalidación (IDTE), comprendiendo la instrucción multifunción IDTE un campo (602) de código de operación que tiene un valor del campo del código de operación que identifica la instrucción como una instrucción IDTE multifunción, siendo la instrucción IDTE multifunción para realizar una primera función o bien una segunda función, comprendiendo la primera función una operaciónde invalidación y borrado, y comprendiendo la segunda función una operación de borrado y no una operación de invalidación; ejecutar la instrucción IDTE multifunción realizando los pasos de: cuando la función de la instrucción IDTE multifunción extraída consiste en la operación de invalidación y borrado, realizar los pasos 1) y 2): 1) invalidar (404) una gama predeterminada de uno o más elementos de tabla de traducción de direcciones, de una tabla de traducción de direcciones, comenzando en un lugar predeterminado de un elemento de la tabla de direcciones; y 2) borrar (505), (508) memorias intermedias de traducción de direcciones de elementos de memorias intermedias de traducción de direcciones asociados con el uno o más elementos invalidados de la tabla de traducción de direcciones; cuando la función de la instrucción IDTE multifunción extraída consiste solamente en una operación de borrado, realizar el paso de: borrar memorias intermedias de traducción de direcciones de elementos de memorias intermedias de traducción de direcciones asociados con el uno o más elementos de la tabla de traducción de direcciones, comprendiendo el uno o más elementos de la tabla de traducción de direcciones una gama predeterminada de uno o más elementos de tabla de traducción de direcciones, de una tabla de traducción de direcciones, comenzando en un lugar predeterminado de un elemento de la tabla de traducción de direcciones.

公开(公告)号：PL1588267T3

公开(公告)日：2008-06-30

申请号：PL04731399

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

公开(公告)号：GB2413876B

公开(公告)日：2006-03-01

申请号：GB0516192

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F12/10

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.