公开(公告)号：WO2004099997A9

公开(公告)日：2005-10-27

申请号：PCT/GB2004001971

申请日：2004-05-06

Applicant: IBM ,  IBM UK ,  SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F9/3824 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109

Abstract: Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.

Abstract translation: 所选存储单元（如存储区域或存储区域）无效。 通过设置位于与要被无效的存储单元相对应的数据结构条目中的无效指示符来促进无效。 此外，清除与无效存储单元或其他所选存储单元相关联的缓冲区条目。 提供了执行无效和/或清除的指令。 此外，与特定地址空间相关联的缓冲区条目将被清除，无任何无效。 这也由指令执行。 该指令可以以软件，硬件，固件或其某种组合来实现，或者可以被仿真。

公开(公告)号：JPH10283178A

公开(公告)日：1998-10-23

申请号：JP4930398

申请日：1998-03-02

Applicant: IBM

Inventor： GETZLAFF KLAUS JOERG ,  LEPPLA BERND ,  PFEFFER ERWIN ,  PFLUEGER THOMAS ,  WITHELM BIRGIT

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To issue an instruction to an execution unit even at the time of a continuous sequence and back-to-back in a random processing system by setting the valid bit of the target operand before the target operand of the instruction becomes usable. SOLUTION: The instruction is taken out from an instruction memory 100 and successively buffered in an instruction cache 101, then the instruction is decoded to a common internal instruction format and then, the instruction is transferred to a reservation station 103. In the reservation station 103, the instruction stands by until issuance to one of function units can be performed. In such a random processing system, the valid bit of the target operand is set before the target operand of the instruction becomes usable. A source operand is generated as the target operand of a preceding instruction and the instruction is immediately issued when the valid bit is set to the entire source operands.

公开(公告)号：JP2002358235A

公开(公告)日：2002-12-13

申请号：JP2002115333

申请日：2002-04-17

Applicant: IBM

Inventor： GAERTNER UTE ,  HAGSPIEL NORBERT ,  LEHNERT FRANK ,  PFEFFER ERWIN ,  SCHELM KERSTIN

IPC: G06F12/1027 ,  G06F12/08 ,  G06F12/10

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system of sharing a TLB2 among CPUs transparently in the CPU architecture and therefore in compliance with the architecture rule. SOLUTION: This invention, in general, refers to a shared memory multiprocessor system of IBM ESA/390 or RS/6000 system, or the like, and in particular refers to the method and the system that share, among a plurality of CPUs, the translation lookaside buffer(TLB2) of second level to improve the performance and reduce a chip area necessary for buffering the result of virtual/absolute address translation. The invented TLB2 configuration includes a plurality of small arrays dedicated for a specific CPU, thus providing an interface for a main array shared among CPUs. The dedicated array is required to meet systematic restrictions and provide a link to a shared array commonly used by a plurality of CPUs.

公开(公告)号：WO2009087133A9

公开(公告)日：2009-09-24

申请号：PCT/EP2009050050

申请日：2009-01-05

Applicant: IBM ,  GREINER DAN ,  GAINEY CHARLES JR ,  HELLER LISA ,  OSISEK DAMIAN ,  PFEFFER ERWIN ,  SLEGEL TIMOTHY ,  WEBB CHARLES

Inventor： GREINER DAN ,  GAINEY CHARLES JR ,  HELLER LISA ,  OSISEK DAMIAN ,  PFEFFER ERWIN ,  SLEGEL TIMOTHY ,  WEBB CHARLES

IPC: G06F12/14 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F12/0215 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/145 ,  G06F2212/1052 ,  G06F2212/654 ,  G06F2212/656 ,  G06F2212/68

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field.

Abstract translation: 提供的是增强的动态地址转换设施。 在一个实施例中，首先获得要被翻译的虚拟地址，并且获得翻译表层级的翻译表的初始起始地址。 基于获得的初始起点，获得段表条目。 段表项被配置为包含格式控制和访问有效性字段。 如果启用格式控制和访问有效性字段，则段表条目还包含访问控制字段，提取保护字段和段帧绝对地址。 仅当访问控制字段与程序状态字或正在执行的程序指令的操作数提供的程序访问键匹配时，才允许存储操作。 如果与虚拟地址相关联的程序访问密钥等于段访问控制字段，则允许获取操作。

公开(公告)号：CY1111466T1

公开(公告)日：2015-08-05

申请号：CY111100318

申请日：2011-03-23

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F12/08

Abstract: Επιλεγείσεςμονάδεςαποθήκευσης, όπωςτμήματααποθήκευσηςή περιοχέςαποθήκευσης, ακυρώνονται. Ηακύρωσηδιευκολύνεταιμετηρύθμισηδεικτώνακύρωσηςτοποθετημένωνστιςκαταχωρήσειςτηςδομήςδεδομένωνπουαντιστοιχούνστιςμονάδεςαποθήκευσηςπουθαακυρωθούν. Επιπροσθέτως, καταχωρήσειςπρόσκαιρηςαποθήκευσηςή άλλεςεπιλεγόμενεςμονάδεςαποθήκευσηςκαθαρίζονται. Παρέχεταιοδηγίαγιαναδιεξάγεταιη ακύρωσηή/καιο καθαρισμός. Επιπλέον, καταχωρήσειςπρόσκαιρηςαποθήκευσηςπουσυνδυάζονταιμεσυγκεκριμένοχώροδιεύθυνσηςκαθαρίζονταιχωρίςοποιαδήποτεακύρωση. Αυτόεπίσηςδιεξάγεταιμετηνοδηγία. Ηοδηγίαμπορείναπραγματοποιηθείσελογισμικό, σεμηχάνημαυπολογιστή, σεπρογράμματααναχαίτισηςή κάποιοσυνδυασμόαυτώνή μπορείνααντιγράφεται.

公开(公告)号：SI2248025T1

公开(公告)日：2012-05-31

申请号：SI200930238

申请日：2009-02-17

Applicant: IBM

Inventor： GREINER DAN ,  HELLER LISA ,  OSISEK DAMIAN ,  PFEFFER ERWIN

IPC: G06F12/00

公开(公告)号：AT491178T

公开(公告)日：2010-12-15

申请号：AT05108510

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

公开(公告)号：DE10002120B4

公开(公告)日：2006-04-20

申请号：DE10002120

申请日：2000-01-20

Applicant: IBM

Inventor： GAERTNER UTE ,  PFEFFER ERWIN ,  SCHELM KERSTIN ,  MACDOUGALL JOHN

IPC: G06F12/1027

Abstract: The basic idea comprised of the present invention is to provide a translation lookaside buffer (TLB) arrangement which advantageously uses two buffers, a small first level TLB1 and a larger second level TLB2. The second level TLB feeds address information to the first level TLB when the desired virtual address is not contained in the first level TLB. According to the invention the second level TLB is structured advantageously comprising two n-way set-associative sub-units of which one, a higher level unit covers some higher level address translation levels and the other one, a lower level unit, covers some lower level translation level. According to the present invention, some address information holds some number of middle level virtual address (MLVA) bits, i.e., 8 bits, for example, being able to serve as an index address covering the address range of the higher level sub-unit. Thus, the same information is used as a tag information in the lower-level sub-unit and is used herein as a quick reference in any look-up operation in order to find the absolute address of the concerned virtual address. Further, the commonly used status bits, like; e.g., valid bits, are used in both TLB structures, too.

公开(公告)号：DE19929050C2

公开(公告)日：2002-01-03

申请号：DE19929050

申请日：1999-06-25

Applicant: IBM

Inventor： GAERTNER UTE ,  HAESS JUERGEN ,  LAUB OLIVER ,  MAURER EBERHARD ,  PFEFFER ERWIN

IPC: G06F9/32 ,  G06F9/38

公开(公告)号：CY1113979T1

公开(公告)日：2016-07-27

申请号：CY131100366

申请日：2013-05-02

Applicant: IBM

Inventor： GREINER DAN ,  HELLER LISA ,  OSISEK DAMIAN ,  SLEGEL TIMOTHY ,  PFEFFER ERWIN ,  WEBB CHARLES

IPC: G06F12/10

Abstract: Αυτόπουπαρέχεταιείναιμίαευκολίαβελτιωμένηςδυναμικήςμεταφράσεωςδιευθύνσεως. Σεμίαυλοποίηση, λαμβάνονται, μίαεικονικήδιεύθυνσηπροςμετάφρασηκαιμίααρχικήδιεύθυνσηπροελεύσεωςενόςπίνακαμεταφράσεωςμίαςιεραρχίαςπινάκωνμεταφράσεως. Χρησιμοποιείταιένατμήμαδείκτητηςεικονικήςδιευθύνσεωςγιαναγίνειαναφοράσεμίαεισαγωγήστονπίνακαμεταφράσεως. Εάνέχειενεργοποιηθείτοπεδίοελέγχουμορφοτύπου, λαμβάνεταιμίαδιεύθυνσηπλαισίουενόςμεγάλουμπλοκδεδομένωνστηνκύριαμνήμηαπότηνεισαγωγήπίνακαμεταφράσεως. Τομεγάλομπλοκδεδομένωνείναιέναμπλοκμεγέθουςτουλάχιστον 1Mbyte. Ηδιεύθυνσηπλαισίουσυνδυάζεταικατόπινμεένατμήμαμετατοπίσεωςτηςεικονικήςδιευθύνσεωςγιανασχηματισθείη μεταφρασθείσαδιεύθυνσηενόςεπιθυμητούμπλοκδεδομένωνεντόςτουμεγάλουμπλοκδεδομένωνστηνκύριαμνήμη. Γίνεταικατόπινπροσπέλασητουεπιθυμητούμεγάλουμπλοκδεδομένωνπουδιευθυνσιοδοτείταιαπότημεταφρασθείσαδιεύθυνση.