公开(公告)号：US3916388A

公开(公告)日：1975-10-28

申请号：US47482574

申请日：1974-05-30

Applicant: IBM

Inventor： SHIMP EVERETT MONTAGUE ,  SLIZ NICHOLAS BERNARD

IPC: G06F9/312 ,  G06F9/315 ,  G06F12/04 ,  G06F15/00

CPC classification number: G06F9/30043 ,  G06F9/30032 ,  G06F9/3816 ,  G06F12/04

Abstract: An improved multibyte data shifting apparatus is disclosed for use in a microprogram controlled data processing system to efficiently shift a multibyte data field accessed from a structured memory where it was stored across the boundary between a first and second memory word, and to load the data field justified, into a processor register. The shifting apparatus is responsive to a first microprogram control word specifying the multibyte data field length, to shift a first plurality of bytes accessed from the first memory word and to load it into a processor register in a position shifted such that the total multibyte field to be accessed will be justified. The amount of shift is determined by a binary adder operating on the low order bits of the storage address and the field length data. The binary adder generates a carry output which indicates that the multibyte field accessed lies across a memory word boundary. The carry output is connected to a branching unit in the microprogram controller causing the controller to branch to a second microprogram control word. The shifting apparatus is then responsive to the second microprogram control word to shift a second plurality of bytes, as the remaining portion of the multibyte field, accessed from the second memory word and to load it justified in the processor register. The multibyte data field is thereby accessed and justified in no more than two control word cycles. Both read and store accessing is accommodated by the invention.

Abstract translation: 公开了一种改进的多字节数据移位装置，用于微程序控制的数据处理系统，以有效地移动从结构化存储器访问的多字节数据字段，其中它被存储在第一和第二存储器字之间的边界上，并且加载数据字段 有理由进入处理器寄存器。 换档装置响应于指定多字节数据字段长度的第一微程序控制字来移动从第一存储器字访问的第一多个字节，并将其加载到处理器寄存器中，使得总多字节字段 被访问是有道理的。 移位量由对存储地址和字段长度数据的低位进行操作的二进制加法器确定。 二进制加法器产生一个进位输出，指示所访问的多字节字段跨越一个存储器字边界。 进位输出连接到微程序控制器中的分支单元，使得控制器分支到第二微程序控制字。 移位装置然后响应于第二微程序控制字来移位第二多个字节，因为多字节字段的剩余部分从第二存储器字访问，并将其加载到处理器寄存器中。 因此，多字节数据字段被访问并且在不超过两个控制字周期内被对齐。 本发明容纳了读取和存储访问。

公开(公告)号：DE2748991A1

公开(公告)日：1978-05-18

申请号：DE2748991

申请日：1977-11-02

Applicant: IBM

Inventor： BONNER BRUCE ROGER ,  SLIZ NICHOLAS BERNARD

IPC: H03M7/00 ,  G06F5/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/30 ,  G06F3/00

Abstract: Data format converting apparatus is described for simultaneously converting multiple bytes of zoned decimal data to packed decimal data or vice versa. In the preferred embodiment, this format converting apparatus is obtained by adding a minimum amount of additional circuitry to a multibyte flow-through type data shifter used for providing the normal data shifting operations in a digital data processor. In particular, a zoned-decimal-to-packed-decimal conversion capability is provided by combining additional switching logic with the normal shifter switching logic for enabling the conductors for nonadjacent data fields on the shifter input data bus to be coupled to the conductors for adjacent data fields on the shifter output data bus. A packed-decimal-to-zoned-decimal conversion capability is provided by adding further switching logic for enabling the conductors for adjacent data fields on the shifter input data bus to be coupled to the conductors for nonadjacent data fields on the shifter output data bus. Control circuitry is provided for selectively enabling either normal data shifting operations or zoned-to-packed format conversion operations or packed-to-zoned format conversion operations. The shifting and format converting hardware is organized so that implementation in the form of large-scale integration circuitry can be accomplished with a minimum number of integrated circuit chips and a minimum number of chip input/output connections per chip.