公开(公告)号：EP1872402A4

公开(公告)日：2008-06-11

申请号：EP06758334

申请日：2006-04-13

Applicant: IBM

Inventor： WARNOCK JAMES D ,  SMITH GEORGE E III

IPC: H01L27/01

CPC classification number: H01L27/1203 ,  H01L27/088 ,  H01L29/7833 ,  H01L29/78615

Abstract: A first or primary field effect transistor ('FET') (620) is separated from a body contact thereto by one or more second FETs (632) that are placed electrically in parallel with the first FET (620). In this way, the body of the first FET (620) can be extended into the region occupied by the second FET (632) to allow contact to be made to the body of the first FET (620). In one embodiment, the gate conductor of the first FET (620) and a gate conductor of the second FET (632) are integral parts of a unitary conductive pattern. The unitary conductive pattern is made desirably small, and can be made as small as the smallest predetermined linewidth for gate conductors on an integrated circuit which includes the body-contacted FET. In this way, area and parasitic capacitance are kept small.

公开(公告)号：WO2006113395A3

公开(公告)日：2007-03-08

申请号：PCT/US2006013987

申请日：2006-04-13

Applicant: IBM ,  WARNOCK JAMES D ,  SMITH GEORGE E III

Inventor： WARNOCK JAMES D ,  SMITH GEORGE E III

IPC: H01L27/01

CPC classification number: H01L27/1203 ,  H01L27/088 ,  H01L29/7833 ,  H01L29/78615

Abstract: A first or primary field effect transistor ("FET") (620) is separated from a body contact thereto by one or more second FETs (632) that are placed electrically in parallel with the first FET (620). In this way, the body of the first FET (620) can be extended into the region occupied by the second FET (632) to allow contact to be made to the body of the first FET (620). In one embodiment, the gate conductor of the first FET (620) and a gate conductor of the second FET (632) are integral parts of a unitary conductive pattern. The unitary conductive pattern is made desirably small, and can be made as small as the smallest predetermined linewidth for gate conductors on an integrated circuit which includes the body-contacted FET. In this way, area and parasitic capacitance are kept small.

Abstract translation: 第一或主要场效应晶体管（“FET”）（620）通过与第一FET（620）并联放置的一个或多个第二FET（632）与其体接触分离。 以这种方式，第一FET（620）的主体可以延伸到由第二FET（632）占据的区域中，以允许与第一FET（620）的主体接触。 在一个实施例中，第一FET（620）的栅极导体和第二FET（632）的栅极导体是整体导电图案的整体部分。 整体式导电图案理想地小，并且可以制成与包括身体接触的FET的集成电路上的栅极导体的最小预定线宽一样小。 以这种方式，面积和寄生电容保持较小。

公开(公告)号：SG77703A1

公开(公告)日：2001-01-16

申请号：SG1999003716

申请日：1999-07-30

Applicant: IBM

Inventor： SMITH GEORGE E III

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/84

Abstract: Disclosed is a type "BC" body contacted SOI transistor and process for making these transistors in a manufacturing environment by providing a structure and process which removes overlay tolerance from the effective transistor width. The width is determined by RX on the top side, but by PC on the other with source and drain connected together. In the preferred embodiment such a structure is used as the top part of the SOI transistor with the bottom part a mirror image of the top part such that the effect of the PC to RX overlay is reversed, and the top part and bottom part are connected by a common body part. For the bottom part an "UP misalignment will make the device with large, while a "DOWN" misalignment will make the device width smaller. Thus, if PC is misalleged with respect to RX, any width errors introduced in the top part of the transistor will be exactly canceled by the bottom part of the transistor. An alternative DOG BONE embodiment is also illustrated which also provides a structure which removes the overlay tolerance from the effective transistor width.