公开(公告)号：CA962952A

公开(公告)日：1975-02-18

申请号：CA145637

申请日：1972-06-26

Applicant: IBM

Inventor： LINDSEY ROYCE D ,  SMITH LARRY G

IPC: B41J5/44 ,  G06F3/023 ,  G11B27/036

Abstract: An efficient system is disclosed for utilization in the storage address log portions of a typewriting system including a multi-page buffer and a substantially larger serial bulk memory. A keyboard-printer is connected to a multi-page buffer. Also connected to the multi-page buffer is a serial bulk memory which, in the preferred embodiment, is a magnetic tape cassette. The operator can temporarily store textual characters in the multi-page buffer and can transfer the buffer contents to the tape in the tape cassette for permanent storage. An address logging system is provided for assigning storage blocks on the tape for reading or recording. Included in this address logging system is an electronic static shift register (SSR) having stored therein indicia representative of the availability or unavailability for storage of each storage block on the tape. Also stored in the SSR of the address logging system are job identifying codes input by the operator from the keyboard as well as storage block address codes corresponding to the particular storage blocks on which are recorded textual characters included in a particular job. After each store or delete operation on one of the storage blocks on the tape, the contents of the SSR are recorded on the first storage block on the tape. Thus, the contents of the log stored on the tape, in the event of power failure which would destroy the contents of both the multi-page buffer and the SSR, are current up to the last completed job.

公开(公告)号：CA983623A

公开(公告)日：1976-02-10

申请号：CA159467

申请日：1972-12-20

Applicant: IBM

Inventor： SMITH LARRY G

IPC: B41J5/30 ,  G06F3/12 ,  G06F17/22 ,  G06F17/24 ,  G06K1/12

公开(公告)号：CA981369A

公开(公告)日：1976-01-06

申请号：CA159470

申请日：1972-12-20

Applicant: IBM

Inventor： LINDSEY ROYCE D ,  SMITH LARRY G

IPC: H03M7/02 ,  B41J5/44 ,  G06F12/00 ,  G06F17/22 ,  G06F17/24 ,  G11C7/00 ,  G11C19/00

Abstract: A system for arranging the memory in an electronic dynamic shift register for performing multiple operations during a memory revolution. Control codes, such as separator and record flags, are input into the shift register memory for defining an input and a revision zone. Upon detecting these control codes during a memory revolution, data codes are input into the input and revision zones and deleted from the revision zone. Another control code, such as a page end code, input into the revision zone defines an output zone. During an output operation data codes in the output zone are output from the record flag through the page end code.