公开(公告)号：US3647041A

公开(公告)日：1972-03-07

申请号：US3647041D

申请日：1970-06-30

Applicant: IBM

Inventor： DAVIS WILLIAM H ,  HORNUNG LOUIS M ,  LINDSEY ROYCE D ,  TANNER HOWARD C

IPC: B41J19/64 ,  B41J5/30

CPC classification number: B41J19/64

Abstract: A system for determining and entering line measure into a justification computer for controlling the format of output copy. During an output operation when there is a necessity for determining line measure, a measure seek code is detected, escapement of the carrier initiated, the escapement of the carrier sensed, and the units of escapement counted. Upon sensing the location of the right margin stop, escapement is terminated. Thereafter the carrier is returned to the position occupied prior to the measure seek code being read. The number of units counted is the line measure which is then used for control of output.

Abstract translation: 一种用于确定和输入线性度量的系统，用于控制输出副本的格式。 在需要确定线路测量的输出操作期间，检测出测量寻道码，启动的载波的擒纵机构，感测到的载波的擒纵机构和擒纵机构的数量。 一旦感测到右边缘挡块的位置，擒纵机构终止。 此后，载波返回到被读取的测量寻找代码之前被占用的位置。 计算的单位数是用于控制输出的线测量。

公开(公告)号：US3611299A

公开(公告)日：1971-10-05

申请号：US3611299D

申请日：1970-02-16

Applicant: IBM

Inventor： LINDSEY ROYCE D ,  MCDONALD WILLIAM L

IPC: G06K1/12 ,  G06F11/00

CPC classification number: G06K1/125

Abstract: A system for use in a keypunch application. Keyed data is recorded onto a magnetic card. To prevent interruption of the keying rhythm during movement of the read-record head from track to track and during card feed, a two-sectioned memory is employed, which through selection of a single address and gated logic allows data to be transferred from one section to the other section without need of buffering or other types of temporary storage or delay. The two-sectioned single address memory is also utilized during verify and duplication operations with, in the case of the latter, the data from a first record being entered from the keyboard into the first section of memory and being transferred to the second section for transfer to the magnetic card. During duplication into a second record from the keyboard, data is transferred back into the first section from the second section through utilization of the single address technique.

公开(公告)号：CA962952A

公开(公告)日：1975-02-18

申请号：CA145637

申请日：1972-06-26

Applicant: IBM

Inventor： LINDSEY ROYCE D ,  SMITH LARRY G

IPC: B41J5/44 ,  G06F3/023 ,  G11B27/036

Abstract: An efficient system is disclosed for utilization in the storage address log portions of a typewriting system including a multi-page buffer and a substantially larger serial bulk memory. A keyboard-printer is connected to a multi-page buffer. Also connected to the multi-page buffer is a serial bulk memory which, in the preferred embodiment, is a magnetic tape cassette. The operator can temporarily store textual characters in the multi-page buffer and can transfer the buffer contents to the tape in the tape cassette for permanent storage. An address logging system is provided for assigning storage blocks on the tape for reading or recording. Included in this address logging system is an electronic static shift register (SSR) having stored therein indicia representative of the availability or unavailability for storage of each storage block on the tape. Also stored in the SSR of the address logging system are job identifying codes input by the operator from the keyboard as well as storage block address codes corresponding to the particular storage blocks on which are recorded textual characters included in a particular job. After each store or delete operation on one of the storage blocks on the tape, the contents of the SSR are recorded on the first storage block on the tape. Thus, the contents of the log stored on the tape, in the event of power failure which would destroy the contents of both the multi-page buffer and the SSR, are current up to the last completed job.

公开(公告)号：CA990410A

公开(公告)日：1976-06-01

申请号：CA181282

申请日：1973-09-18

Applicant: IBM

Inventor： LINDSEY ROYCE D

IPC: G06F11/00 ,  G11B20/18

Abstract: An encoding and decoding technique for detecting loss of phase and/or bit sync, and resynchronizing following an error. Both detection and resynchronization are accomplished on a per character basis. With seven bits being used per character, the bits making up each character are phase encoded in a conventional manner. For defining each character, an additional 1/2 bit time is added between bits 7 and 1 and encoded such that a corrective flux reversal may occur at 1/2 T (where T equals the normal intracharacter bit time), a transition must not occur at T (normal data time), and the 1 bit of the next character must occur at 11/2 T. Digital data separation is used to define corrective flux reversals and data bits, and any flux transitions outside the limits defined are considered errors. During decoding, the data separation logic is resynchronized on each detected data transition by the sync signal. With this method, if either phase or bit sync is lost within any character, an error condition will be detected at least before bit 1 of the next character.

公开(公告)号：CA981369A

公开(公告)日：1976-01-06

申请号：CA159470

申请日：1972-12-20

Applicant: IBM

Inventor： LINDSEY ROYCE D ,  SMITH LARRY G

IPC: H03M7/02 ,  B41J5/44 ,  G06F12/00 ,  G06F17/22 ,  G06F17/24 ,  G11C7/00 ,  G11C19/00

Abstract: A system for arranging the memory in an electronic dynamic shift register for performing multiple operations during a memory revolution. Control codes, such as separator and record flags, are input into the shift register memory for defining an input and a revision zone. Upon detecting these control codes during a memory revolution, data codes are input into the input and revision zones and deleted from the revision zone. Another control code, such as a page end code, input into the revision zone defines an output zone. During an output operation data codes in the output zone are output from the record flag through the page end code.