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公开(公告)号：US3782674A
公开(公告)日：1974-01-01
申请号：US3782674D
申请日：1972-10-17
Applicant: IBM
Inventor： SMITH R
Abstract: A kinematic extensible truss mechanism comprising a first set of truss members arranged in a parallelogram with pivots at each of the junctures of the truss members, and a second set of truss members arranged in a parallelogram with pivots at each of the junctures of the second set of truss members. Two of the pivots of the first set coincide with two of the pivots of the second set, and at least one rigid extension projects from one of the truss members of the second set substantially at right angles thereton. An arm is pivotally connected to the rigid extension and connected for rotation to a pivot of the first set of truss members which is not common to the first and second set of truss members. In this manner movement of one of the truss members of one of the sets relative to another member of the other of the sets maintains parallelism of the one truss member to the other when relative motion occurs in a first direction, and results in an elevation of the one relative to the other when relative motion occurs in the opposite direction.
Abstract translation: 一种运动学可伸展桁架机构，包括在桁架构件的每个接合处以枢轴布置成平行四边形的第一组桁架构件，以及在第二组的每个接合处以平行四边形布置的枢轴的第二组桁架构件 的桁架成员。 第一组的枢轴中的两个与第二组的两个枢轴重合，并且至少一个刚性延伸部从第二组的桁架构件中的一个基本上以直角横向伸出。 臂被枢转地连接到刚性延伸部并且连接用于旋转到第一组桁架构件的枢轴，这对于第一和第二组桁架构件是不常见的。 以这种方式，相对于另一组中的另一个的组中的一个的桁架构件中的一个的运动在相对于第一方向发生相对运动时保持一个桁架构件到另一个的桁架构件的平行度，并且导致 当相对运动发生在相反方向时，相对于另一个相对运动。
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Patent Agency Ranking2.发明授权Signal processor instruction for non-blocking communication between data processing units 失效信号处理器指令数据处理单元之间的非阻塞通信
公开(公告)号：US3787891A
公开(公告)日：1974-01-22
申请号：US3787891D
申请日：1972-07-03
Applicant: IBM
CPC classification number: G06F9/4881
Abstract: Control initiating instruction SIGNAL PROCESSOR is used to transfer a select control initiating order designated by the instruction from an initiating unit which executes the instruction to a designated respondent unit which interprets the order. If the respondent unit detects an invalid order or other specific exception circumstance it immediately returns indications of specific exception status to the initiating unit. This status is retained in a register specified by the instruction. The entire transaction is completed during the ''''short'''' control sequence of execution of the instruction. Hence the participating units and their interconnections are subject to efficient pre-emptive interruption without further delays for ''''sense'''' communication of specific exception status. The identity of the respondent unit and an addend factor of the control initiating order are prepared for quick transfer in registers of the initiating unit designated by information in the instruction. The order representation is formed by adding a portion of the immediate instruction and the above addend factor. Optionally contents of another prepared register designated by the instruction information are subject to transfer with the order code as an ancillary output parameter. Another option permits the user to direct the instruction order to itself for diagnostic or other program usage.
Abstract translation: 控制发起指令SIGNAL PROCESSOR用于将执行该指令的发起单元指令指定的选择控制启动顺序传送到解释顺序的指定回应单元。 如果被访者单元检测到无效的订单或其他特定的异常情况，则它立即向启动单元返回特定异常状态的指示。 该状态保留在指令指定的寄存器中。 整个交易在指令执行的“短”控制顺序完成。 因此，参与单位及其相互联系将受到有效的先发制人中断，而不会进一步延迟具体异常状态的“有意义”沟通。 准备应答单元的身份和控制启动顺序的加数因子，用于在由指令中的信息指定的启动单元的寄存器中进行快速传输。 订单表示是通过添加直接指令的一部分和上述加数因子来形成的。 可选地，由指令信息指定的另一个准备寄存器的内容将以订单代码作为辅助输出参数进行转移。 另一种选择允许用户将指令命令引导到自身进行诊断或其他程序使用。
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公开(公告)号：SE341935B
公开(公告)日：1972-01-17
申请号：SE636466
申请日：1966-05-10
Applicant: IBM
Inventor： SMITH R , BEAUSOLEIL W , CLARK W , HILL P
Abstract: 1,142,465. Data processors. INTERNATIONAL BUSINESS MACHINES CORP. 2 May, 1966 [12 May, 1965], No. 19173/66. Heading G4A. In a data processing system, access to an address in peripheral storage is permitted or prevented in accordance with the result of a comparison of the address with information developed from a stored catalogue of addresses available to the current programme. A CPU (central processing unit) with associated main core storage can communicate via channels with external devices viz. input/output units and storage units (e.g. disc units). A stored catalogue, in the main storage or an external storage unit, specifies for each data file in an external storage unit, the boundaries of the file (high and low, cylinder and head numbers in the case of a disc unit) and the types of writing and reading access permitted to the associated problem programme. Other problem programmes are denied all access. The control unit of an external storage unit, on being selected for storage access, receives the relevant information from the catalogue byte by byte, the bytes being passed on respective odd counts of a counter in the control unit, from an in - put/output register which initially receives them, to respective further registers in the control unit. The access attempt is terminated and the CPU interrupted and informed of the reason, if the input/output register does not hold zero on any even count, during this. In the absence of this error indication, the cylinder and head numbers of the desired address are received into the input/output register in turn and compared with the boundary bytes in turn, under control of the counter, in the following order (disc unit): cylinder high, cylinder low, head high, head low. The required cylinder and head are selected as soon as their respective comparisons say yes, but if any comparison says no, the access attempt is terminated without further comparisons and the CPU interrupted as before. Termination &c. will also occur if the access is of a non-permitted type, as determined in the control unit, or if the input/output register does not hold zero at certain times before and after the comparisons. Cylinder selection involves finding the difference between the present and desired cylinder numbers, in an adder. A circuit is provided to detect any attempt to set said further registers with more than one set of information from the catalogue. In a modification mentioned, the catalogue supplies two bits specifically allowing or forbidding movement from the current head and cylinder respectively, instead of the boundary data. Conventional arrangements for selection of an external device, including transmission of status back, are described.
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公开(公告)号：SE329515B
公开(公告)日：1970-10-12
申请号：SE547265
申请日：1965-04-27
Applicant: IBM
Abstract: 1,083,171. Control of input/output equipment. INTERNATIONAL BUSINESS MACHINES CORPORATION. April 21, 1965 [April 27, 1964], No. 16743/65. Heading G4A. In data processing apparatus, any one of a plurality of input/output (I/O) units can be connected to any one of a plurality of I/O control units through control and data lines by electronic and relay switches respectively when said switches, which are respective to the pair of units, are actuated by the I/O control unit. Selection in this way of one I/O unit by an I/O control unit prevents subsequent selection of the same I/O unit by another I/O control unit until it is free. In the particular embodiment, a computer sends a 9-bit byte (includes parity bit) to one of four " tape control " units to cause it to select one of 16 magnetic tape I/O units. Four of the bits of the byte identify the tape I/O unit, one of these bits (" high order " bit) choosing one set of 8 tape units and the other 3 bits being decoded into a 1-out-of-8 energization to choose one tape unit within that set. By means of switches, the two subsets of 4 tape units within each set may be effectively interchanged (" swapped "). Two further switches enable the two sets of 8 to be effectively interchanged. Further switches enable selection of any particular tape I/O unit(s) by any particular tape control unit(s) to be prevented. When a " tape control " unit has selected a tape I/O unit, command, " sense " (see below) and data bytes (the latter including a parity bit) may be passed between them. After passage of one such byte, the I/O unit is normally free to be selected by another " tape control " unit but the computer may prevent this with a "chain" " signal. The " sense " information, provided by the tape I/O unit, includes model number (indicating data rate effectively), byte size, status, whether tape file is protected &c. Effective interchange of tape units (see above) requires interchange of status lines and this is done by changing the position of a printed circuit card. Longitudinal parity check bytes may be recorded on the tape. Error correction may be done in the " tape control " units after reading from the tape.
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公开(公告)号：ZA7407113B
公开(公告)日：1976-06-30
申请号：ZA7407113
申请日：1974-11-05
Applicant: IBM
CPC classification number: G06F12/1036 , G06F12/145
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