公开(公告)号：US3735368A

公开(公告)日：1973-05-22

申请号：US3735368D

申请日：1971-06-25

Applicant: IBM

Inventor： BEAUSOLEIL W

IPC: G06F11/10 ,  G11C29/00 ,  G11C11/00

CPC classification number: G11C29/76 ,  G06F11/1024

Abstract: A computer memory, most particularly a monolithic memory, may be constructed of components which contain defective bit cells. During the production process, the monolithic chips are sorted into groups in accordance with the chip sector which contains one or more defective cells. The chips are then mounted on memory cards, with all of the chips having a defect in a given chip sector being mounted on a corresponding card sector. The cards, each of which is produced in a substantially identical manner, are then assembled into a complete memory. The address wiring of the memory is provided in such a manner as to ensure that no given memory word, or defined group of bits within a memory word, contains within it more than one memory cell that is known or suspected to be defective. Means are also provided for deriving from the address of any given memory word the bit location within said word of a defective or suspicious bit. In one embodiment shown herein, the suspect bit is bypassed in favor of a redundant bit provided within the memory system. In another embodiment described herein, the suspect bit is utilized just as if it were a good bit, but, upon detection of an error, the suspect bit will be presumed to be in error.

Abstract translation: 计算机存储器，特别是单片存储器，可以由包含有缺陷位单元的组件构成。 在生产过程中，根据包含一个或多个缺陷单元的芯片扇区将单片芯片分组成一组。 然后将这些芯片安装在存储卡上，所有芯片在给定芯片扇区中具有缺陷，安装在相应的卡片扇区上。 然后，以基本相同的方式产生每个卡的卡被组装成完整的存储器。 提供存储器的地址布线以确保没有给定的存储器字或存储器字中的定义的位组在其内包含多于一个已知或怀疑是有缺陷的存储器单元。 还提供了用于从任何给定存储器字的地址导出有缺陷或可疑位的所述字内的位位置的装置。 在本文所示的一个实施例中，可疑位被旁路以有利于提供在存储器系统内的冗余位。 在本文描述的另一实施例中，可疑位被利用，好像它是一个好位，但是在检测到错误时，怀疑位将被认为是错误的。

公开(公告)号：US3765001A

公开(公告)日：1973-10-09

申请号：US3765001D

申请日：1971-11-15

Applicant: IBM

Inventor： BEAUSOLEIL W

IPC: G11C8/12 ,  G11C29/00 ,  G11C11/40

CPC classification number: G11C29/76 ,  G11C8/12

Abstract: In the production of monolithic memory chips used in computer storage devices a certain percentage is rejected in production as containing one or more defective bit cells on the chip. These almost perfect chips are arranged on a memory card bit so that all of the bit cards of a particular memory product are identical to those sections containing defective bit cells. The valid cells are logically arranged in contiguous address locations by translation logic which converts the address before it is presented to the memory bit cards. Addresses presented to the logic are re-ordered such that all addresses that, untranslated, would have selected a defective area of a chip, after being translated select a non-defective area of a chip.

Abstract translation: 在用于计算机存储设备中的单片存储器芯片的生产中，在芯片上包含一个或多个有缺陷的位单元的生产中一定百分比被拒绝。 这些几乎完美的芯片布置在存储卡位上，使得特定存储器产品的所有位卡与包含有缺陷位单元的部分相同。 有效的单元格通过平移逻辑在逻辑上排列在连续的地址位置，该逻辑将地址提供给存储位卡之前将其转换。 重新排列呈现给逻辑的地址，使得未经翻译的所有地址在被翻译后选择芯片的缺陷区域选择芯片的无缺陷区域。

公开(公告)号：US3789247A

公开(公告)日：1974-01-29

申请号：US3789247D

申请日：1972-07-03

Applicant: IBM

Inventor： BEAUSOLEIL W ,  HO I ,  YU H

IPC: G11C27/04 ,  G06F3/00 ,  G06F12/00 ,  G11C19/28 ,  H01L21/339 ,  H01L27/105 ,  H01L29/762 ,  H01L11/14

CPC classification number: G06F3/007 ,  G11C19/285 ,  G11C19/287 ,  H01L27/1057

Abstract: The specification describes charge coupled devices in a bidirectional shift register and having a dynamic ordering capability. Charge coupled devices are shown in a semiconductor structure with FET amplifying circuits, uniquely adapted for bidirectional operation by means of a circuit which changes the order of occurrence of the clocking pulses. The density of charge coupled devices is preserved together with improved access time resulting from bidirectional operation and dynamic ordering.

Abstract translation: 本说明书描述了双向移位寄存器中的电荷耦合器件，并具有动态排序能力。 电荷耦合器件以具有FET放大电路的半导体结构示出，其独特地适用于通过改变时钟脉冲的发生次序的电路进行双向操作。 电荷耦合器件的密度与由双向操作和动态排序产生的改进的访问时间保持在一起。

公开(公告)号：US3740723A

公开(公告)日：1973-06-19

申请号：US3740723D

申请日：1970-12-28

Applicant: IBM

Inventor： BEAUSOLEIL W ,  HO I ,  PRICER W

IPC: G06F12/08 ,  G11C11/415 ,  G11C19/00 ,  G11C9/00 ,  G11C11/34

CPC classification number: G11C19/00 ,  G06F12/0864 ,  G11C11/415

Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.

公开(公告)号：US3724749A

公开(公告)日：1973-04-03

申请号：US3724749D

申请日：1971-04-15

Applicant: IBM

Inventor： BEAUSOLEIL W

IPC: G06K1/04 ,  G06K1/08

CPC classification number: G06K1/04

Abstract: A high-speed column locate feature whereby a keypunch operator may select at random any predetermined column location on a unit record card and control the card punching to either automatically duplicate or skip at high speed to the selected column. A prepunched program card is provided in conjunction with auxiliary column-select keys. The program card has pre-punched coded patterns which are selectable by the column-select keys. By the appropriate choice of column-select keys and the wiring of the keys, a field definition is impressed upon keypunch field definition logic. When the SKIP or DUP control key is depressed, the card being fed automatically feeds the length of the field defined by the field impressed upon the field definition logic.

Abstract translation: 一种高速列定位功能，其中键击操作者可以随机选择单位记录卡上的任何预定列位置，并且控制卡冲孔以高速自动复制或跳过到所选列。 预先加工的程序卡与辅助列选择键一起提供。 程序卡具有可以通过列选择键选择的预打孔编码图案。 通过适当选择列选择键和键的布线，字段定义在关键字字段定义逻辑上印象深刻。 当按下SKIP或DUP控制键时，自动馈送的卡会自动输入由字段定义逻辑上所打印的字段定义的字段的长度。

公开(公告)号：US3714637A

公开(公告)日：1973-01-30

申请号：US3714637D

申请日：1970-09-30

Applicant: IBM

Inventor： BEAUSOLEIL W

IPC: G11C11/413 ,  G06F12/16 ,  G11C8/00 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00 ,  G11C11/40

CPC classification number: G11C29/76 ,  G11C8/00

Abstract: Transformation logic is provided in the addressing portion of a computer memory to permit the memory to be constructed of components containing defective bit cells. In the production of monolithic memory chips used in computer storage devices, a certain percentage is rejected in production as containing one or more defective bit cells on the chip. This apparatus arranges the almost perfect chips on a memory bit card so that all of the bit cards of a particular memory product are identical as to those sections containing defective bit cells. The valid cells are logically arranged in contiguous address locations by transformation logic which converts the address before it is presented to the memory bit cards. This circuitry places the defective bit positions in high order address locations which are not accessed.

公开(公告)号：US3858189A

公开(公告)日：1974-12-31

申请号：US31940872

申请日：1972-12-29

Applicant: IBM

Inventor： WALKER E ,  BEAUSOLEIL W ,  KEEFE G

IPC: G11C11/14 ,  G01R33/09 ,  G11C19/08

CPC classification number: G11C19/0866 ,  G01R33/09

Abstract: A plurality of magneto-resistive sensing elements are connected in series and positioned adjacent magnetic bubble domain propagation paths in a compressor circuit. If a data representing bubble is injected into the beginning of the circuit, each bubble already present is forced over to the next idler position. As the bubbles pass the sensing elements their magnetization vectors are rotated producing corresponding changes in the resistance values of the sensors, which may be easily detected as a large magnitude signal indicating the presence of a data bubble.

Abstract translation: 多个磁阻感测元件串联连接并定位在压缩机电路中的与气泡扩散路径相邻的位置。 如果将表示气泡的数据注入到电路的开始处，则已经存在的每个气泡被迫过渡到下一个惰轮位置。 当气泡通过感测元件时，它们的磁化矢量被旋转，从而产生传感器的电阻值的相应变化，这可以容易地被检测为指示数据气泡存在的大幅度信号。

公开(公告)号：US3781826A

公开(公告)日：1973-12-25

申请号：US3781826D

申请日：1971-11-15

Applicant: IBM

Inventor： BEAUSOLEIL W

IPC: G11C29/00 ,  G11C29/04 ,  G11C11/40 ,  G11C15/00

CPC classification number: G11C29/76

Abstract: A monolithic computer memory constructed of monolithic chips which contain defective bit cells. During the production process, the chips are sorted into groups in accordance with the chip sector or quadrant which contains one or more defective cells. The chips are then mounted on modules and the modules are placed on memory cards, with all of the chips having a defect in a given chip sector being mounted in a corresponding card sector. The cards, each of which is produced in a substantially identical manner, are then assembled into a complete memory. The valid cells are logically arranged in contiguous address locations by transformation logic which converts the address before it is presented to the memory bit cards. Addresses presented to the logic are re-ordered such that all addresses that, untranslated, would have selected a defective area of a chip, after being translated select a non-defective area of a chip.

Abstract translation: 由单片芯片构成的单片计算机存储器，其中包含有缺陷的位单元。 在生产过程中，根据包含一个或多个缺陷单元的芯片扇区或象限将芯片分组成组。 然后将芯片安装在模块上，并且将模块放置在存储卡上，所有芯片在给定芯片扇区中具有缺陷，安装在相应的卡扇区中。 然后，以基本相同的方式产生每个卡的卡被组装成完整的存储器。 有效的单元格通过转换逻辑在逻辑上排列在连续的地址位置，该地址在将地址提供给存储位卡之前将其转换。 重新排列呈现给逻辑的地址，使得未经翻译的所有地址在被翻译后选择芯片的缺陷区域选择芯片的无缺陷区域。

公开(公告)号：US3766534A

公开(公告)日：1973-10-16

申请号：US3766534D

申请日：1972-11-15

Applicant: IBM

Inventor： BEAUSOLEIL W ,  PHELPS B

IPC: G11C19/00 ,  G06F7/78 ,  G06F12/00 ,  G11C7/00 ,  G11C15/04 ,  G11C19/18 ,  G11C19/28

CPC classification number: G06F7/78 ,  G11C15/04 ,  G11C19/188 ,  G11C19/287

Abstract: A data storage unit in which words of data including the word addresses are stored in groups of shiftable matrices, the groups of matrices being operable on a signal requesting access to repetitively shift their contents to other matrix positions in various loops, some of which include a position from which a word may be accessed and some of which exclude the access position. The bits in a data word are distributed among groups of matrices, each group generally containing only one bit of a given word. Each group is logically divided into a plurality of sectors, with each sector containing bits from several words. Controls are provided for varying the shifting in the various loops such that the positions of some or all of the sectors are dynamically reordered so that the proximity of each of the sectors to the access position is approximately or exactly the order in which the sectors were last requested, and so that the word bits within the sectors are also positioned so that their proximity to the access position is approximately or exactly the order in which they were last requested, thus reducing average access time in programs involving considerable repeated reference to a limited group of sectors and/or words in the memory, and substantially reducing worst-case access time for all situations.

Abstract translation: 一种数据存储单元，其中包括字地址的数据的字被存储在可移位矩阵的组中，所述矩阵组可以在请求访问的信号上操作以将它们的内容重复地移动到各种循环中的其他矩阵位置，其中一些包括 可以访问单词的位置，其中一些排除访问位置。 数据字中的位分布在矩阵组中，每组通常只包含给定字的一个位。 每组逻辑上划分为多个扇区，每个扇区包含来自多个单词的位。 提供控制以改变各种环路中的移位，使得部分或全部扇区的位置被动态重新排序，使得每个扇区到访问位置的接近度大致或恰好是扇区最后的顺序 并且使得扇区中的字位也被定位成使得它们与访问位置的接近度近似或恰好地是它们最后请求的顺序，从而减少涉及相当多地重复引用有限组的程序中的平均访问时间 的存储器中的扇区和/或字，并且大大减少了所有情况下的最坏情况访问时间。

公开(公告)号：CA929271A

公开(公告)日：1973-06-26

申请号：CA83256

申请日：1970-05-21

Applicant: IBM

Inventor： BROWN P ,  BEAUSOLEIL W

IPC: G06F13/10 ,  G06F13/42