公开(公告)号：WO2004070773A3

公开(公告)日：2004-10-28

申请号：PCT/GB2004000434

申请日：2004-02-04

Applicant: IBM ,  IBM UK ,  BUFFET PATRICK ,  COHN JOHN ,  GROSSELFINGER KEVIN ,  LICHTENSTEIGER SUSAN ,  SMITH WILLIAM

Inventor： BUFFET PATRICK ,  COHN JOHN ,  GROSSELFINGER KEVIN ,  LICHTENSTEIGER SUSAN ,  SMITH WILLIAM

IPC: H01L20060101 ,  H01L27/00 ,  H01L27/02 ,  H01L27/118 ,  H03K19/00 ,  H03K19/173

CPC classification number: H01L27/11898 ,  H01L27/0207

Abstract: An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of (and evenly spaces) the power switches according to the size of the serviceable area to which each of the power switches can provide power. The size of the power switches are matched to the current and voltage that will be provided by the power buses. The size of the serviceable area to which each of the power switches can provide power is dependent upon the size of the power switches.

Abstract translation: 集成电路结构在电压岛内具有至少一个电压岛和功率开关模式。 该模式根据每个电源开关可以提供电力的可用区域的大小确定电源开关的数量（并且均匀地间隔）。 电源开关的大小与电源总线提供的电流和电压相匹配。 每个电源开关可以提供电力的可服务区域的大小取决于电源开关的大小。

公开(公告)号：JP2004111967A

公开(公告)日：2004-04-08

申请号：JP2003319044

申请日：2003-09-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AUDET JEAN ,  BUDELL TIMOTHY ,  BUFFET PATRICK

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0265 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/0352 ,  H05K2201/09627 ,  H05K2201/09736 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To provide an electronic packaging device with high density and low resistance signal lines.
SOLUTION: In the present invention, an electronic packaging assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.
COPYRIGHT: (C)2004,JPO

公开(公告)号：AT509371T

公开(公告)日：2011-05-15

申请号：AT04707972

申请日：2004-02-04

Applicant: IBM

Inventor： BUFFET PATRICK ,  COHN JOHN ,  GROSSELFINGER KEVIN ,  LICHTENSTEIGER SUSAN ,  SMITH WILLIAM

IPC: H01L27/02 ,  H01L20060101 ,  H01L27/00 ,  H01L27/118 ,  H03K19/00 ,  H03K19/173

Abstract: An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of (and evenly spaces) the power switches according to the size of the serviceable area to which each of the power switches can provide power. The size of the power switches are matched to the current and voltage that will be provided by the power buses. The size of the serviceable area to which each of the power switches can provide power is dependent upon the size of the power switches.