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公开(公告)号：ES2153354T3
公开(公告)日：2001-03-01
申请号：ES92310528
申请日：1992-11-18
Applicant: IBM
Inventor： ASADA SHIGEKI , SOHDA MASAYUKI , YASUDA HIROAKI
Abstract: A display system for converting N bit signals each representing 2 gray scale levels, to M bit signals representing 2 gray levels (where N is an integer larger than or equal to 2 and M is an integer satisfying N>M>/=1) comprises a register (1) for separating each of the N bit signals into higher order M bits and N-M bits. 2 tables (5,6,7,8) each store a distinctive set of PxQ modification values satisfying PxQ>/=2 . A control device (12) selects one of the tables as a function of the N-M bits. A comparator (31) detects a difference between a first set of modification values and a second set of modification values of the selected table. An exchanger (32) exchanges the first set of modification values and the second set of modification values to generate a modified table from the selected table. An adder (9) adds the M bits of one N bit signal and each of the modification values of the selected table to generate a first set of PxQ M bit signals, and adds the M bits of next N bit signal and each of the modification values of the modified table to generate a second set of PxQ M bit signals. The first and second sets of M bit signals are then supplied to a display device having 2 gray levels. This permits the addition of pel lines to the picture displayed on the LCD device to bring the aspect ratio of the LCD device into line with that of a CRT device without introducing inconsistent gray levels into the picture.
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公开(公告)号：CA2079352C
公开(公告)日：1997-05-13
申请号：CA2079352
申请日：1992-09-24
Applicant: IBM
Inventor： ASADA SHIGEKI , SOHDA MASAYUKI , YASUDA HIROAKI
Abstract: A personal computer generates first gray level signals each dot of which is represented by N bits (where N is an integer larger than or equal to 2) representing 2N (the Nth. power of 2) gray levels. The first gray level signal is supplied to a CRT display, each dot of which displays 2N (the Nth. power of 2) gray levels. Now, the CRT is replaced by an LCD, each dot of which displays 2M (the Mth. power of 2) gray levels. An algorithm converts the first gray level signal of N bits representing 2N gray levels to second gray level signals representing 2M gray levels. The second gray level signals are applied to the LCD. The invention solves a problem raised when an algorithm is used to generate an image for LCDs and that image is expanded in a vertical direction.
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Patent Agency Ranking
公开(公告)号：DE69231642D1
公开(公告)日：2001-02-22
申请号：DE69231642
申请日：1992-11-18
Applicant: IBM
Inventor： ASADA SHIGEKI , SOHDA MASAYUKI , YASUDA HIROAKI
Abstract: A display system for converting N bit signals each representing 2 gray scale levels, to M bit signals representing 2 gray levels (where N is an integer larger than or equal to 2 and M is an integer satisfying N>M>/=1) comprises a register (1) for separating each of the N bit signals into higher order M bits and N-M bits. 2 tables (5,6,7,8) each store a distinctive set of PxQ modification values satisfying PxQ>/=2 . A control device (12) selects one of the tables as a function of the N-M bits. A comparator (31) detects a difference between a first set of modification values and a second set of modification values of the selected table. An exchanger (32) exchanges the first set of modification values and the second set of modification values to generate a modified table from the selected table. An adder (9) adds the M bits of one N bit signal and each of the modification values of the selected table to generate a first set of PxQ M bit signals, and adds the M bits of next N bit signal and each of the modification values of the modified table to generate a second set of PxQ M bit signals. The first and second sets of M bit signals are then supplied to a display device having 2 gray levels. This permits the addition of pel lines to the picture displayed on the LCD device to bring the aspect ratio of the LCD device into line with that of a CRT device without introducing inconsistent gray levels into the picture.
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公开(公告)号：SG43735A1
公开(公告)日：1997-11-14
申请号：SG1996000333
申请日：1992-11-18
Applicant: IBM
Inventor： SOHDA MASAYUKI , YASUDA HIROAKI , ASADA SHIGEKI
Abstract: A display system for converting N bit signals each representing 2 gray scale levels, to M bit signals representing 2 gray levels (where N is an integer larger than or equal to 2 and M is an integer satisfying N>M>/=1) comprises a register (1) for separating each of the N bit signals into higher order M bits and N-M bits. 2 tables (5,6,7,8) each store a distinctive set of PxQ modification values satisfying PxQ>/=2 . A control device (12) selects one of the tables as a function of the N-M bits. A comparator (31) detects a difference between a first set of modification values and a second set of modification values of the selected table. An exchanger (32) exchanges the first set of modification values and the second set of modification values to generate a modified table from the selected table. An adder (9) adds the M bits of one N bit signal and each of the modification values of the selected table to generate a first set of PxQ M bit signals, and adds the M bits of next N bit signal and each of the modification values of the modified table to generate a second set of PxQ M bit signals. The first and second sets of M bit signals are then supplied to a display device having 2 gray levels. This permits the addition of pel lines to the picture displayed on the LCD device to bring the aspect ratio of the LCD device into line with that of a CRT device without introducing inconsistent gray levels into the picture.
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公开(公告)号：DE69231642T2
公开(公告)日：2001-06-21
申请号：DE69231642
申请日：1992-11-18
Applicant: IBM
Inventor： ASADA SHIGEKI , SOHDA MASAYUKI , YASUDA HIROAKI
Abstract: A display system for converting N bit signals each representing 2 gray scale levels, to M bit signals representing 2 gray levels (where N is an integer larger than or equal to 2 and M is an integer satisfying N>M>/=1) comprises a register (1) for separating each of the N bit signals into higher order M bits and N-M bits. 2 tables (5,6,7,8) each store a distinctive set of PxQ modification values satisfying PxQ>/=2 . A control device (12) selects one of the tables as a function of the N-M bits. A comparator (31) detects a difference between a first set of modification values and a second set of modification values of the selected table. An exchanger (32) exchanges the first set of modification values and the second set of modification values to generate a modified table from the selected table. An adder (9) adds the M bits of one N bit signal and each of the modification values of the selected table to generate a first set of PxQ M bit signals, and adds the M bits of next N bit signal and each of the modification values of the modified table to generate a second set of PxQ M bit signals. The first and second sets of M bit signals are then supplied to a display device having 2 gray levels. This permits the addition of pel lines to the picture displayed on the LCD device to bring the aspect ratio of the LCD device into line with that of a CRT device without introducing inconsistent gray levels into the picture.
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公开(公告)号：CA2157970A1
公开(公告)日：1996-03-23
申请号：CA2157970
申请日：1995-09-11
Applicant: IBM
Inventor： NISHINO HIRONARI , NISHIMURA HIROKAZU , SOHDA MASAYUKI
Abstract: To prevent errors caused by jitters and delays, in separating and fetching the synchronous signal from a video signal to which a synchronous signal has been added a sync-on-green signal is fetched from a branch line branched on the way of a signal line connecting the output pin of a video amp and an A/D converter and is connected to the plus side input pin of a comparator. That is, to the plus input pin of the comparator there is input a voltage corresponding to a brightness signal amplified by the video amp and also shifted by an offset voltage. Also, to the minus input pin of the comparator there is input a threshold voltage for detecting the falling edge of said synchronous signal. If the voltage corresponding to the video signal is less than the threshold voltage, the comparator will determine that the synchronous signal was detected and output a logic low level (L) signal.
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公开(公告)号：CA2079352A1
公开(公告)日：1993-06-04
申请号：CA2079352
申请日：1992-09-24
Applicant: IBM
Inventor： ASADA SHIGEKI , SOHDA MASAYUKI , YASUDA HIROAKI
Abstract: A display system for converting N bit signals each representing 2 gray scale levels, to M bit signals representing 2 gray levels (where N is an integer larger than or equal to 2 and M is an integer satisfying N>M>/=1) comprises a register (1) for separating each of the N bit signals into higher order M bits and N-M bits. 2 tables (5,6,7,8) each store a distinctive set of PxQ modification values satisfying PxQ>/=2 . A control device (12) selects one of the tables as a function of the N-M bits. A comparator (31) detects a difference between a first set of modification values and a second set of modification values of the selected table. An exchanger (32) exchanges the first set of modification values and the second set of modification values to generate a modified table from the selected table. An adder (9) adds the M bits of one N bit signal and each of the modification values of the selected table to generate a first set of PxQ M bit signals, and adds the M bits of next N bit signal and each of the modification values of the modified table to generate a second set of PxQ M bit signals. The first and second sets of M bit signals are then supplied to a display device having 2 gray levels. This permits the addition of pel lines to the picture displayed on the LCD device to bring the aspect ratio of the LCD device into line with that of a CRT device without introducing inconsistent gray levels into the picture.
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