-
-
公开(公告)号：JPH05241545A
公开(公告)日：1993-09-21
申请号：JP31881391
申请日：1991-12-03
Applicant: IBM
Inventor： ASADA SHIGEKI , HAYATA MASAYUKI , YASUDA HIROAKI
Abstract: PURPOSE: To prevent the quality deterioration of images at different half-tone levels caused by the addition of a horizontal line or vertical column by providing an M-bit signal generating means and a means which supplies first and second sets of M-bit signals to a display device of a specific half-tone level. CONSTITUTION: The display system is provided with a means which generates first and second sets of M-bit signals respectively composed of PXQ pieces of signals and supplies the first and second sets of M-bit signals to an LCD device 25 at a 2M half-tone level. When operations are started from a picture element position (0, 0), a controller 12 first resets registers 1 and 4, an X counter 27, and Y counters 28 and 35. In this case, the controller 12 operates an odd column discriminating circuit 29, a line pattern generating circuit 36, and a comparator circuit 37, because the horizontal line of the LCD device 25 is added, namely, inserted. Therefore, the problem of image lines caused by dither tables 6-8 can be solved.
-
公开(公告)号：JPS62159972A
公开(公告)日：1987-07-15
申请号：JP29340485
申请日：1985-12-27
Applicant: IBM
Inventor： ASADA SHIGEKI , HASEGAWA MEGUMI
-
公开(公告)号：DE69231642T2
公开(公告)日：2001-06-21
申请号：DE69231642
申请日：1992-11-18
Applicant: IBM
Inventor： ASADA SHIGEKI , SOHDA MASAYUKI , YASUDA HIROAKI
Abstract: A display system for converting N bit signals each representing 2 gray scale levels, to M bit signals representing 2 gray levels (where N is an integer larger than or equal to 2 and M is an integer satisfying N>M>/=1) comprises a register (1) for separating each of the N bit signals into higher order M bits and N-M bits. 2 tables (5,6,7,8) each store a distinctive set of PxQ modification values satisfying PxQ>/=2 . A control device (12) selects one of the tables as a function of the N-M bits. A comparator (31) detects a difference between a first set of modification values and a second set of modification values of the selected table. An exchanger (32) exchanges the first set of modification values and the second set of modification values to generate a modified table from the selected table. An adder (9) adds the M bits of one N bit signal and each of the modification values of the selected table to generate a first set of PxQ M bit signals, and adds the M bits of next N bit signal and each of the modification values of the modified table to generate a second set of PxQ M bit signals. The first and second sets of M bit signals are then supplied to a display device having 2 gray levels. This permits the addition of pel lines to the picture displayed on the LCD device to bring the aspect ratio of the LCD device into line with that of a CRT device without introducing inconsistent gray levels into the picture.
-
公开(公告)号：CA2079352A1
公开(公告)日：1993-06-04
申请号：CA2079352
申请日：1992-09-24
Applicant: IBM
Inventor： ASADA SHIGEKI , SOHDA MASAYUKI , YASUDA HIROAKI
Abstract: A display system for converting N bit signals each representing 2 gray scale levels, to M bit signals representing 2 gray levels (where N is an integer larger than or equal to 2 and M is an integer satisfying N>M>/=1) comprises a register (1) for separating each of the N bit signals into higher order M bits and N-M bits. 2 tables (5,6,7,8) each store a distinctive set of PxQ modification values satisfying PxQ>/=2 . A control device (12) selects one of the tables as a function of the N-M bits. A comparator (31) detects a difference between a first set of modification values and a second set of modification values of the selected table. An exchanger (32) exchanges the first set of modification values and the second set of modification values to generate a modified table from the selected table. An adder (9) adds the M bits of one N bit signal and each of the modification values of the selected table to generate a first set of PxQ M bit signals, and adds the M bits of next N bit signal and each of the modification values of the modified table to generate a second set of PxQ M bit signals. The first and second sets of M bit signals are then supplied to a display device having 2 gray levels. This permits the addition of pel lines to the picture displayed on the LCD device to bring the aspect ratio of the LCD device into line with that of a CRT device without introducing inconsistent gray levels into the picture.
-
Patent Agency Ranking
公开(公告)号：ES2153354T3
公开(公告)日：2001-03-01
申请号：ES92310528
申请日：1992-11-18
Applicant: IBM
Inventor： ASADA SHIGEKI , SOHDA MASAYUKI , YASUDA HIROAKI
Abstract: A display system for converting N bit signals each representing 2 gray scale levels, to M bit signals representing 2 gray levels (where N is an integer larger than or equal to 2 and M is an integer satisfying N>M>/=1) comprises a register (1) for separating each of the N bit signals into higher order M bits and N-M bits. 2 tables (5,6,7,8) each store a distinctive set of PxQ modification values satisfying PxQ>/=2 . A control device (12) selects one of the tables as a function of the N-M bits. A comparator (31) detects a difference between a first set of modification values and a second set of modification values of the selected table. An exchanger (32) exchanges the first set of modification values and the second set of modification values to generate a modified table from the selected table. An adder (9) adds the M bits of one N bit signal and each of the modification values of the selected table to generate a first set of PxQ M bit signals, and adds the M bits of next N bit signal and each of the modification values of the modified table to generate a second set of PxQ M bit signals. The first and second sets of M bit signals are then supplied to a display device having 2 gray levels. This permits the addition of pel lines to the picture displayed on the LCD device to bring the aspect ratio of the LCD device into line with that of a CRT device without introducing inconsistent gray levels into the picture.
-
公开(公告)号：DE3686521T2
公开(公告)日：1993-03-11
申请号：DE3686521
申请日：1986-06-13
Applicant: IBM
Inventor： ASADA SHIGEKI , YANAGISAWA HIROSHI
IPC: G06F3/00 , H04N1/028 , H04N1/04 , H04N1/17 , H04N1/19 , H04N3/14 , H04N5/335 , H04N5/341 , H04N5/372
Abstract: The invention is devised to start application of clock pulses to a shift register in a sensor unit of an image scanner in synchronization with a read signal from a processor in a method for controlling the image scanner so as to enable to easily and directly fetch video data outputted from the shift register into the processor as its input data without using a DMA (Direct Memory Access) method or a program loop method that requires special measures in aspects of hardware and software.In addition, the invention is devised to provide a data disposing cycle in the operation mode of the shift register in addition to the data reading cycle, so that, even when interruption from others causes the operation of the processor fetching the video data from the shift register to exceed a predetermined scanning time before completion of the operation, the data disposing cycle is inserted right after completion of the operation to dispose high level data that has been sensed for a long period of time by a photosensor of the sensor unit, and normal level data or image information properly representing an image being scanned is obtained.Furthermore, the invention reduces significantly processing load of the processor with a simple hardware constitution by adding the operation of a run length counter etc. so as to enable high speed linear data compression.
-
公开(公告)号：CA2079352C
公开(公告)日：1997-05-13
申请号：CA2079352
申请日：1992-09-24
Applicant: IBM
Inventor： ASADA SHIGEKI , SOHDA MASAYUKI , YASUDA HIROAKI
Abstract: A personal computer generates first gray level signals each dot of which is represented by N bits (where N is an integer larger than or equal to 2) representing 2N (the Nth. power of 2) gray levels. The first gray level signal is supplied to a CRT display, each dot of which displays 2N (the Nth. power of 2) gray levels. Now, the CRT is replaced by an LCD, each dot of which displays 2M (the Mth. power of 2) gray levels. An algorithm converts the first gray level signal of N bits representing 2N gray levels to second gray level signals representing 2M gray levels. The second gray level signals are applied to the LCD. The invention solves a problem raised when an algorithm is used to generate an image for LCDs and that image is expanded in a vertical direction.
-
公开(公告)号：DE3686521D1
公开(公告)日：1992-10-01
申请号：DE3686521
申请日：1986-06-13
Applicant: IBM
Inventor： ASADA SHIGEKI , YANAGISAWA HIROSHI
IPC: G06F3/00 , H04N1/028 , H04N1/04 , H04N1/17 , H04N1/19 , H04N3/14 , H04N5/335 , H04N5/341 , H04N5/372
Abstract: The invention is devised to start application of clock pulses to a shift register in a sensor unit of an image scanner in synchronization with a read signal from a processor in a method for controlling the image scanner so as to enable to easily and directly fetch video data outputted from the shift register into the processor as its input data without using a DMA (Direct Memory Access) method or a program loop method that requires special measures in aspects of hardware and software.In addition, the invention is devised to provide a data disposing cycle in the operation mode of the shift register in addition to the data reading cycle, so that, even when interruption from others causes the operation of the processor fetching the video data from the shift register to exceed a predetermined scanning time before completion of the operation, the data disposing cycle is inserted right after completion of the operation to dispose high level data that has been sensed for a long period of time by a photosensor of the sensor unit, and normal level data or image information properly representing an image being scanned is obtained.Furthermore, the invention reduces significantly processing load of the processor with a simple hardware constitution by adding the operation of a run length counter etc. so as to enable high speed linear data compression.
-
公开(公告)号：SG43735A1
公开(公告)日：1997-11-14
申请号：SG1996000333
申请日：1992-11-18
Applicant: IBM
Inventor： SOHDA MASAYUKI , YASUDA HIROAKI , ASADA SHIGEKI
Abstract: A display system for converting N bit signals each representing 2 gray scale levels, to M bit signals representing 2 gray levels (where N is an integer larger than or equal to 2 and M is an integer satisfying N>M>/=1) comprises a register (1) for separating each of the N bit signals into higher order M bits and N-M bits. 2 tables (5,6,7,8) each store a distinctive set of PxQ modification values satisfying PxQ>/=2 . A control device (12) selects one of the tables as a function of the N-M bits. A comparator (31) detects a difference between a first set of modification values and a second set of modification values of the selected table. An exchanger (32) exchanges the first set of modification values and the second set of modification values to generate a modified table from the selected table. An adder (9) adds the M bits of one N bit signal and each of the modification values of the selected table to generate a first set of PxQ M bit signals, and adds the M bits of next N bit signal and each of the modification values of the modified table to generate a second set of PxQ M bit signals. The first and second sets of M bit signals are then supplied to a display device having 2 gray levels. This permits the addition of pel lines to the picture displayed on the LCD device to bring the aspect ratio of the LCD device into line with that of a CRT device without introducing inconsistent gray levels into the picture.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.017 seconds)
