公开(公告)号：DE3381653D1

公开(公告)日：1990-07-19

申请号：DE3381653

申请日：1983-07-22

Applicant: IBM

Inventor： LAVALLEE RUSSELL WILLIAM ,  RYAN PHILIP MEADE ,  SOLLITTO JR

IPC: G06F12/08

Abstract: A hierarchical memory system is disclosed comprising at least one dual-ported memory level (9, 19), each port having access to a separate bidirectional data bus (1, 2). The port (9) facing the higher memory levels is equipped with a pair of data buffers (5, 6) having a bit width equal to the bit width of a single row of cells in the storage array (4) contained within the dual-ported level. One buffer (output) is loaded in one cycle from the array. The other buffer (input) is emptied in one cycle into the array. Both buffers interact with the higher memory level independently of the transferring of data through the other of the dual ports. Thus, contention for the use of bus facilities and contention for memory cycles are greatly reduced in the transferring of data between the memory levels.