公开(公告)号：EP0096030A4

公开(公告)日：1985-07-01

申请号：EP82900447

申请日：1981-12-17

Applicant: IBM

Inventor： RYAN PHILIP MEADE

IPC: G06F11/00 ,  G11C29/00 ,  G01R31/28

CPC classification number: G11C29/88 ,  G06F11/076

Abstract: Apparatus for mapping and classifying the faulty bits of a large computer memory. Known data is read into the memory (1) and then the data stored in the memory is read out in a predetermined sequence (17, 18). The data read out is compared (10) with the known written data and the mismatches (errors) are counted (11, 12). Based upon the number of errors counted and the known sequence in which the stored data is read out, the type of fault is determined, e.g., a failure of an entire bit line, a failure of an entire word line, etc., and a status byte is established (7) representing the fault type. The status byte is useful in determining a reconfiguration of the memory whereby the faulty memory bits are scattered among accessed data words in such a way that available error correcting capability can correct the remaining faulty bits in each data word.

公开(公告)号：DE3173738D1

公开(公告)日：1986-03-20

申请号：DE3173738

申请日：1981-10-29

Applicant: IBM

Inventor： BENJAMIN CHARLES EPHRAIM ,  CRAWFORD DAVID JAMES ,  DAVIS DONALD EUGENE ,  MOORE RICHARD DAVID ,  RYAN PHILIP MEADE ,  WEBER EDWARD VICTOR

IPC: G03F1/00 ,  H01J37/304 ,  G03B41/00

公开(公告)号：DE3584859D1

公开(公告)日：1992-01-23

申请号：DE3584859

申请日：1985-05-24

Applicant: IBM

Inventor： RYAN PHILIP MEADE ,  AICHELMANN JR

IPC: G06F12/16 ,  G06F11/07 ,  G06F11/10 ,  G06F11/00

公开(公告)号：DE3381653D1

公开(公告)日：1990-07-19

申请号：DE3381653

申请日：1983-07-22

Applicant: IBM

Inventor： LAVALLEE RUSSELL WILLIAM ,  RYAN PHILIP MEADE ,  SOLLITTO JR

IPC: G06F12/08

Abstract: A hierarchical memory system is disclosed comprising at least one dual-ported memory level (9, 19), each port having access to a separate bidirectional data bus (1, 2). The port (9) facing the higher memory levels is equipped with a pair of data buffers (5, 6) having a bit width equal to the bit width of a single row of cells in the storage array (4) contained within the dual-ported level. One buffer (output) is loaded in one cycle from the array. The other buffer (input) is emptied in one cycle into the array. Both buffers interact with the higher memory level independently of the transferring of data through the other of the dual ports. Thus, contention for the use of bus facilities and contention for memory cycles are greatly reduced in the transferring of data between the memory levels.

公开(公告)号：DE2424313A1

公开(公告)日：1975-01-02

申请号：DE2424313

申请日：1974-05-18

Applicant: IBM

Inventor： GILL CHARLES DANA ,  RYAN PHILIP MEADE

IPC: H01J37/305 ,  G06F17/15 ,  G06F17/17 ,  G06F17/18 ,  H01J37/304 ,  H01L21/00 ,  H01L21/027 ,  G01R25/00 ,  H01L21/82

Abstract: In semiconductor manufacture, very accurate patterns must be formed in the photoresist on the surface of the semiconductor material. Chips are formed on a semiconductor wafer utilizing a beam of charged particles to expose the photoresist material on the surface of the semiconductor. If the plurality of chips, is to have the same characteristics and pattern, it is necessary that the electrons or beam of charged particles be moved such that any point within the field to which the beam is applied is always reached by the same history. This requires that patterns produced by an electron beam be properly registered with respect to previously generated patterns. This registration is accomplished by scanning previously placed registration marks on the chip with a beam of electrons and monitoring the reflected or back-scattered electrons to determine where the beam crosses said registration marks. The method disclosed herein is a system of processing the signals encountered during beam contact with the registration marks on the chip usually at the four corners thereof, whereby the location of the marks is accurately determined. This is accomplished by first improving the signal to noise ratio of the detected signal followed by a rapid cross-correlation between the averaged signal and another signal having certain specific and especially desirable characteristics. The final step utilizes a least squares curve fitting procedure tuned up to extract the essential parameter, that is the center of the cross-correlation, with a minimum of on-line computation.

公开(公告)号：DE3380795D1

公开(公告)日：1989-12-07

申请号：DE3380795

申请日：1983-05-27

Applicant: IBM

Inventor： RYAN PHILIP MEADE

IPC: G06F12/16 ,  G11C29/00 ,  G06F11/00

Abstract: A method is disclosed for operating a fault tolerant memory system which is provided with a fault alignment exclusion mechanism of the type where a permute vector controls the relationship between each chip of a column array (12) and the positions of a column buffer register (20). The method allows the assignment of a new permute vector to the fault alignment mechanism even though the memory is operating and storing user data. The method rearranges the data in the affected column (e.g. 12) by transferring data in one chip to another chip in the column through a buffer (20) under the control of the old and new permute vectors. The transfer operation involves transferring the data at the same bit position from each chip in the column to the buffer under the control of the old permute vector and then transferring the data from the buffer to the same bit positions in other chips in the column determined by the new permute vector. The memory is then returned to the user for normal operation. If the column buffer (20) contains less positions than the number of chips in the associated column array (12), the buffers (21) of other columns (13) may be used in addition, to adapt the effective buffer size to the size of the chip array column.

公开(公告)号：DE3176883D1

公开(公告)日：1988-10-27

申请号：DE3176883

申请日：1981-12-17

Applicant: IBM

Inventor： RYAN PHILIP MEADE

IPC: G06F11/00 ,  G11C29/00 ,  G01R31/28

Abstract: In addition to mapping the faults in a large memory, at high speeds, the apparatus classifies the mapped faults according to type. It is applicable where the memory comprises an array of semi-conductor chips and the accessed data words comprise bits from respective chips. Known data is entered into a memory and then the data stored in the memory is read out in a predetermined sequence. This is then compared with the known written data. The mismatches (errors) are counted on the two counters. Based on the number of errors counted, and the known sequence in which the data is read out, the type of fault is determined. The memory array is scanned first by successive word lines and then by successive bit lines within each of a number of chips.

公开(公告)号：DE2805371A1

公开(公告)日：1978-08-24

申请号：DE2805371

申请日：1978-02-09

Applicant: IBM

Inventor： PFEIFFER HANS CHRISTIAN ,  RYAN PHILIP MEADE ,  WEBER EDWARD VICTOR

IPC: H01J37/147 ,  H01J37/09 ,  H01J37/30 ,  H01L21/027