公开(公告)号：US3808462A

公开(公告)日：1974-04-30

申请号：US31052772

申请日：1972-11-29

Applicant: IBM

Inventor： PARRISH J ,  SPAMPINATO D ,  TERMAN L

IPC: G11C19/18 ,  G11C19/28 ,  H03K19/096 ,  H03K23/08

CPC classification number: H03K19/0963 ,  G11C19/184 ,  G11C19/28

Abstract: An inverter incorporating a pair of complementary field effect transistors and a pair of Schottky barrier diodes disposed in series with the complementary transistors is disclosed. The gates of the complementary transistors are connected in parallel to a pulsed source which provides positive and negative inputs to the inverter. First and second pulsed sources are connected to the inverter which, during an ENABLE cycle, provide voltages of opposite polarity to the inverter which, operating in a common source mode, charges an output to one of the source potentials. During a DISABLE cycle, the potential at the output is locked at a node by applying to the inverter potentials complementary to those initially applied to the inverter. A shift register stage consisting of the arrangement just described and an inverted inverter is also disclosed. When this shift register stage is actuated, during the ENABLE portion of a given cycle, one inverter is enabled while the other is disabled and, during the DISABLE portion of the given cycle, the other inverter is enabled while the first inverter is disabled. Also included are embodiments which are operable in a static mode as well as a cynamic mode.

Abstract translation: 公开了一种包含一对互补场效应晶体管和与互补晶体管串联布置的一对肖特基势垒二极管的反相器。 互补晶体管的栅极并联连接到向逆变器提供正和负输入的脉冲源。 第一和第二脉冲源连接到逆变器，在启动循环期间，在逆变器中提供与反相器极性相反的电压，其在共同的源模式下工作，将输出充电到一个源极电位。 在DISABLE循环期间，输出端的电位通过施加到与最初施加到逆变器的逆变器电位互补的逆变器电位而锁定在节点处。 还公开了由刚刚描述的布置和反相逆变器组成的移位寄存器级。 当该移位寄存器级被激活时，在给定周期的ENABLE部分期间，一个反相器被使能，而另一个被禁用，并且在给定周期的禁用部分期间，在禁用第一反相器时，使能另一个反相器。 还包括可在静态模式和动态模式下操作的实施例。

公开(公告)号：US3834959A

公开(公告)日：1974-09-10

申请号：US26787972

申请日：1972-06-30

Applicant: IBM

Inventor： DENNARD R ,  SPAMPINATO D

IPC: H01L27/10 ,  H01L21/00 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/00 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78 ,  H01L7/50

CPC classification number: H01L29/495 ,  H01L21/00 ,  H01L21/823406 ,  H01L27/088 ,  H01L29/00 ,  H01L29/4916

Abstract: A PROCESS FOR THE SIMULTANEOUS FORMATION OF SELFALIGNED SILICON GATES AND ALUMINUM GATES HAVING SELFALIGNED CHANNEL REGIONS ON THE SAME WAFER IS DISCLOSED. BASICALLY, THE PROCESS CONSISTS OF THE DEPOSITION OF SUCCESSIVE LAYERS OF SILICON NITRIDE AND POLYCRYSTALLINE SILICON OVER THICK AND THIN SILICON DIOXIDE REGIONS WHICH ARE DISPOSED ON THE SURFACE OF A SEMICONDUCTOR WAFER. POLYSILICON GATES ARE DELINEATED IN THE THIN OXIDE REGIONS. SUBSEQUENTLY, A CHEMICALLY VAPOR DEPOSITED SILICON DIOXIDE LAYER IS FORMED OVER THE SURFACE OF THE EXPOSED SILICON NITRIDE LAYER AND OVER THE POLYCRYSTALLINE SILICON GATE GEGIONS. AT THIS POINT, THE CVD OXIDE IS DELINEATED TO FORM AN OXIDE MASK WHICH WILL PERMIT THE REMOVAL OF SILICON NITRIDE DOWN TO THE THIN OXIDE AT CERTAIN REGIONS WHERE DIFFUSION WINDOWS ARE TO BE FORMED IN EXPOSED THIN OXIDE REGIONS WHICH ARE SUBSEQUENTLY REMOVED BY A DIP ETCH. WHILE THE EXPOSED THIN OXIDE REGIONS ARE MASKED BY EITHER SILICON NITRIDE PORTIONS OR POLYCRYSTALLINE SILICON GATE REGIONS, THE MASKING REGIONS OF CVD OXIDE WHICH PROTECTED THE SILICON NITRIDE LAYER ARE SIMULTANEOUSLY REMOVED BY THE DIP ETCH WHICH OPENS THE DIFFUSION WINDOWS IN THE THIN OXIDE REGIONS. AFTER A DIFFUSION STEP WHICH INCLUDES DEPOSITION OF A PHOSPHORUS DOPANT IN THE DIFFUSION WINDOWS FROM THE VAPOROUS PHASE AND A DRIVE-IN STEP, A THERMAL OXIDATION STEP IS CARRIED OUT WHICH COVERS THE DIFFUSED WINDOW REGIONS AND THE POLYSILICON GATES AND THICK OXIDE REGIONS LEAVING THE EXPOSED NITRIDE PORTIONS UNAFFECTED. IN A SUBSEQUENT MASKING STEP, DIFFUSION CONTACT WINDOWS AND SILICON GATES CONTACT WINDOWS ARE OPENED. THEN, METALLIZATION IS DEPOSITED EVERYWHERE AND DELINEATED TO FORM METAL GATES AND CONTACTS TO BOTH DIFFUSIONS AND SILICON GATES. METAL IS DELINEATED AND FORMED IN EACH OF THE EXPOSED SILICON NITRIDE REGIONS ONE OF WHICH IS A SELF-ALIGNED CHANNEL REGION FOR A METAL GATE FIELD-EFFECT TRANSISTOR. OTHER METAL GATES FOR A CHARGE COUPLED DEVICE ARE POSITIONED BY VIRTUE OF THE PRESENCE OF ADJACENT POLYSILICON GATES AND ARE INSULATED FROM THE SUBSTRATE BY A THIN OXIDE AND NITRIDE LAYER AND FROM THE SILICON GATES BY A LAYER OF THERMALLY GROWN SILICON DIOXIDE ON THE SURFACE OF THE SILICON GATES. THE RESULTING STRUCTURE INCLUDES A METAL GATE FIELD-EFFECT TRANSISTOR, A SELF-ALIGNED SILICON GATE FIELD-EFFECT TRANSISTOR, AND A CHARGE COUPLED DEVICE ON THE SAME WAFER. BY USING AN ADDITIONAL MASKING STEP OVER THAT REQUIRED FOR THE FORMATION OF SILICON SELF-ALIGNED GATES ALONE, METAL GATES WHICH ARE EITHER SELF-ALIGNED BY VIRTUE OF ADJACENT POLYSILICON GATES OR BY VIRTUE OF THE PRESENCE OF A SELF-ALIGNED CHANNEL ARE THUS OBTAINED. IN ADDITION, A RANDOM ACCESS CHARGE COUPLED DEVICE WHICH INCORPORATES A METAL TRANSFER GATE AND A POLYSILICON STORAGE PLATE IS ALSO DISCLOSED. THE STRUCTURE RESULTS FROM THE ABOVE DESCRIBED FABRICATION PROCESS AND IS STRUCTURALLY UNIQUE IN THAT THE METAL GATE IS DISPOSED IMMEDIATELY ADJACENT TO A DIFFUSION REGION WHICH ITSELF IS DISPOSED UNDER A THICK OXIDE LAYER. IN ADDITION, THE POLYCRYSTALLINE SILICON STORAGE PLATE IS SPACED FROM THE METAL GATE BY A LAYER OF THERMALLY GROWN SILICON DIOXIDE.

公开(公告)号：US3716724A

公开(公告)日：1973-02-13

申请号：US3716724D

申请日：1971-06-30

Applicant: IBM

Inventor： PARRISH J ,  SPAMPINATO D ,  TERMAN L

IPC: G11C19/18 ,  G11C19/28 ,  H03K19/096 ,  G11C19/00

CPC classification number: H03K19/0963 ,  G11C19/184 ,  G11C19/28

Abstract: An inverter incorporating a pair of complementary field effect transistors and a pair of Schottky barrier diodes disposed in series with the complementary transistors is disclosed. The gates of the complementary transistors are connected in parallel to a pulsed source which provides positive and negative inputs to the inverter. First and second pulsed sources are connected to the inverter which, during an ENABLE cycle, provide voltages of opposite polarity to the inverter which, operating in a common source mode, charges an output to one of the source potentials. During a DISABLE cycle, the potential at the output is locked at a node by applying to the inverter potentials complementary to those initially applied to the inverter. A shift register stage consisting of the arrangement just described and an inverted inverter is also disclosed. When this shift register stage is actuated, during the ENABLE portion of a given cycle, one inverter is enabled while the other is disabled and, during the DISABLE portion of the given cycle, the other inverter is enabled while the first inverter is disabled. Also included are embodiments which are operable in a static mode as well as a dynamic mode.

Abstract translation: 公开了一种包含一对互补场效应晶体管和与互补晶体管串联布置的一对肖特基势垒二极管的反相器。 互补晶体管的栅极并联连接到向逆变器提供正和负输入的脉冲源。 第一和第二脉冲源连接到逆变器，在启动循环期间，在逆变器中提供与反相器极性相反的电压，其在共同的源模式下工作，将输出充电到一个源极电位。 在DISABLE循环期间，输出端的电位通过施加到与最初施加到逆变器的逆变器电位互补的逆变器电位而锁定在节点处。 还公开了由刚刚描述的布置和反相逆变器组成的移位寄存器级。 当该移位寄存器级被激活时，在给定周期的ENABLE部分期间，一个反相器被使能，而另一个被禁用，并且在给定周期的禁用部分期间，在禁用第一反相器时，使能另一个反相器。 还包括可在静态模式和动态模式下操作的实施例。

公开(公告)号：BR7700762A

公开(公告)日：1977-10-11

申请号：BR7700762

申请日：1977-02-07

Applicant: IBM

Inventor： HELLER L ,  SPAMPINATO D

IPC: G11C11/41 ,  G11C7/06 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03F3/45 ,  H03K3/356 ,  H03F7/00

公开(公告)号：SE358763B

公开(公告)日：1973-08-06

申请号：SE47469

申请日：1969-01-15

Applicant: IBM

Inventor： SPAMPINATO D ,  TERMAN L ,  GAENSSLEN F

IPC: G11C11/402 ,  G11C11/40

Abstract: 1,224,937. Transistor bi-stable circuits. INTERNATIONAL BUSINESS MACHINES CORP. 11 Dec., 1968 [15 Jan., 1968], No. 58872/68. Heading H3T. [Also in Division G4] A memory cell comprises a pair of crosscoupled FETs forming a bi-stable circuit, in which the OFF transistor provides a backward biased PN junction in the leakage path between its substrate and the gate electrode of the ON FET. A pair of backward biased PN junction devices are connected to the gate electrode of each FET, having a higher leakage current than the PN junction of the OFF FET. In Fig. 1A the READ and WRITE operations are as described for Specification 1,224,936. However, the charge on the ON FET gate of the bi-stable circuit is maintained during the quiescent period by means of a leakage current path existing, e.g. via the biased substrate 39 and region 16 of the switching FET 14 through region 11 and substrate 8 of OFF FET 3. The resistance of the reverse biased PN junction of the FET 14 is deliberately made much lower than that of FET 3, Figs. 1B, 1C (not shown), such that a voltage of approximately -VS exists at the gate 12 of the ON FET 2 thus maintaining its charge. The leakage path via the other FETs 13 and 2 ensures that FET 3 is kept OFF by maintaining a substantially zero voltage at its gate. The transconductance (gm) of the storage FETs is made greater than that of the switching FETs so that during READ out, the high voltage existing across the switching FET keeps the gate voltage of the OFF FET below threshold value.