公开(公告)号：US3789312A

公开(公告)日：1974-01-29

申请号：US3789312D

申请日：1972-04-03

Applicant: IBM

Inventor： HELLER L ,  VOGEL N

IPC: H03F3/185 ,  G11C7/06 ,  H03K5/02 ,  H03K19/096 ,  H03F3/16

CPC classification number: G11C7/067 ,  H03K19/096

Abstract: Low level pulses in the order of 100 millivolts or less can be detected and amplified regardless of variations in the voltage required to turn on the active device used in the amplifier. This is achieved by coupling an active device between a capacitor and a capacitively loaded output line, charging the output line to a reference voltage, applying a level setting voltage to the device to turn on the device; charging the capacitor to a voltage substantially equivalent to the level setting voltage to turn off the device while maintaining it such that any input signal superimposed on the level setting voltage will cause the device to again turn on and discharge the capacitively loaded output line thereby amplifying and inverting the superimposed input signal. The invention is particularly useful for sensing random access integrated semiconductor memories. The invention may be employed in either bipolar or field effect transistor technologies.

Abstract translation: 无论打开放大器中使用的有源器件所需的电压变化如何，都可以检测和放大大小为100毫伏的低电平脉冲。 这通过将有源器件耦合在电容器和电容负载输出线之间来实现，将输出线充电到参考电压，向器件施加电平设置电压以接通器件; 将电容器充电到基本上等于电平设定电压的电压以关闭器件，同时保持它，使得叠加在电平设置电压上的任何输入信号将使器件再次导通并放电电容负载的输出线，从而放大和 反转叠加的输入信号。

公开(公告)号：US3796933A

公开(公告)日：1974-03-12

申请号：US3796933D

申请日：1971-11-10

Applicant: IBM

Inventor： ARNETT P ,  HELLER L ,  STAPPER C

IPC: G11C27/04 ,  H01L21/339 ,  H01L29/423 ,  H01L29/43 ,  H01L29/762 ,  H01L29/768 ,  H01L11/14

CPC classification number: H01L29/42396 ,  H01L29/435 ,  H01L29/76866

Abstract: A charge-coupled semiconductor device for transmitting information in the form of mobile charges through a depletion layer which comprises an electrode structure on the surface of a semiconductor body that has within it an elongated region containing an impurity gradient. When the body is biased to create a depletion under the region and packets of charges are introduced into the body near the region, the charges will under the influence of the field gradients in the depletion layer be caused to pass through the body, in a known period of time. If due to space charge broadening the charge packets slowly spread out, they may be regrouped by applying a single clock pulse to the electrode structure, which will create sharply defined potential wells under the impurity gradient. The device is particularly useful as both a delay line and as a simple, fast, reliable, memory array.

公开(公告)号：US3764906A

公开(公告)日：1973-10-09

申请号：US3764906D

申请日：1971-10-01

Applicant: IBM

Inventor： HELLER L

IPC: G11C11/413 ,  G01R19/155 ,  G01R29/24 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4094 ,  G11C11/4099 ,  G11C19/28 ,  G11C29/00 ,  G11C29/04 ,  G11C29/56 ,  G01R1/00 ,  H02M3/06

CPC classification number: G11C19/285 ,  G11C11/404 ,  G11C11/4094 ,  G11C11/4099

Abstract: The amount of charge stored in a charge storage system can be transferred with negligible loss from the storage system to a charge detector without regard to the size of any distributed capacitance present on the line transferring the charge. This is achieved by charging a detector capacitor and the capacitance of the transfer line, to a reference voltage, allowing the stored charge system and the transfer line capacitance to equalize at a voltage level below the reference voltage, and transferring charge from the detector capacitor to the line capacitance and the charge storage system to return the line and the charge storage system to the reference voltage of charge. The voltage remaining on the detector capacitor is then equal to the original state of charge in the storage system. A particular circuit for performing this method in conjunction with semiconductor memory arrays is also disclosed.

Abstract translation: 存储在电荷存储系统中的电荷量可以以从存储系统到电荷检测器的可忽略的损耗传输，而不考虑传输电荷的线路上存在的任何分布电容的大小。 这是通过将检测器电容器和传输线的电容充电到参考电压来实现的，允许存储的充电系统和传输线电容在低于参考电压的电压电平下均衡，并将电荷从检测器电容器转移到 线路电容和充电存储系统将线路和充电存储系统返回到充电参考电压。 检测电容器上剩余的电压等于存储系统中的原始充电状态。

公开(公告)号：BR7908298A

公开(公告)日：1980-09-16

申请号：BR7908298

申请日：1979-12-18

Applicant: IBM

Inventor： HELLER L

IPC: G11C17/00 ,  G11C11/35 ,  G11C14/00 ,  G11C16/04 ,  G11C19/28 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/112 ,  G11C11/34 ,  H01L29/00

公开(公告)号：BR7700762A

公开(公告)日：1977-10-11

申请号：BR7700762

申请日：1977-02-07

Applicant: IBM

Inventor： HELLER L ,  SPAMPINATO D

IPC: G11C11/41 ,  G11C7/06 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03F3/45 ,  H03K3/356 ,  H03F7/00

公开(公告)号：BR8006769A

公开(公告)日：1981-04-28

申请号：BR8006769

申请日：1980-10-21

Applicant: IBM

Inventor： VOGL N JR ,  HARROUN T ,  HELLER L

IPC: G11C27/04 ,  G11C19/28 ,  H01L21/339 ,  H01L27/105 ,  H01L29/762 ,  G11C11/40

Abstract: An SPS Serial-Parallel-Serial charge coupled device (CCD) memory system is provided wherein a single tap, preferably a storage node, on an input serial or shift register (10) is connected to the input of a plurality of parallel shift registers (14) through a fan out circuit (D) and the output of the plurality of parallel shift registers is connected to a single tap, preferably a storage node, on an output serial or shift register (12) through a fan in circuit (E).

公开(公告)号：CA966229A

公开(公告)日：1975-04-15

申请号：CA156033

申请日：1972-11-08

Applicant: IBM

Inventor： ARNETT P ,  STAPPER C ,  HELLER L

IPC: G11C27/04 ,  H01L21/339 ,  H01L29/423 ,  H01L29/43 ,  H01L29/762 ,  H01L29/768

Abstract: 1383977 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 18 Oct 1972 [10 Nov 1971] 47952/72 Heading H1K In a semi-conductor device, such as a shift register or delay line, utilizing the drift of an injected group 30 of minority-charge carriers through a depletion region 23À1 induced in a substrate 10À1 beneath an electrode structure 20À1, there is provided a graded-impurityconcentration region 17À1 of the same conductivity type as the substrate 10À1. The region 17À1 is graded in such a way that in the presence of the appropriate operating voltages on the substrate electrode 21À1, electrode structure 20À1, injecting electrode 15À1 and detecting electrode 16À1. The boundary of the depletion region 23À1 extends parallel to the device surface. In the Si shift register illustrated the electrode structure 20À1 comprises a plurality of interconnected A1 strips capacitively coupled to the ion implanted region 17À1 through a SiO2 layer 18À1. For P-type material a negative bias on the substrate electrode 21À1 induces the depletion region 23À1, the presence of the grounded strips 20À1 producing shallow potential wells 25 which are rapidly filled with injected charge-carriers. A subsequently injected charge-carrier group 30 will drift along the depletion region 23À1, but will tend to become progressively loss spatially localized due to space charge spreading. The group 30 is periodically reshaped by the application of a positive clock pulse to the electrode structure 20À1. Such a pulse temporarily deepens the potential walls 25, causing the drifting group 30 to be trapped and hence relocalized. Using this techique charge-carrier groups may be directed around carriers and in opposed directions. In a simplified embodiment constituting a delay line the electrode structure 20À1 is replaced by a single continuous electrode (20), Fig. 1 (not shown), overlying the whole length of the graded region (17À1), there being in this case no localized potential walls to reshape an injected pulse.