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    BLACKOUT LOGIC FOR DUAL EXECUTION UNIT PROCESSOR
    3.
    发明专利
    BLACKOUT LOGIC FOR DUAL EXECUTION UNIT PROCESSOR 未知

    公开(公告)号：CA2123448C

    公开(公告)日：1998-10-13

    申请号：CA2123448

    申请日：1994-05-12

    Applicant: IBM

    Inventor： RAY DAVID S ,  SPENCER ALEXANDER K

    IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F15/16

    Abstract: An apparatus and method provides additional logic in both execution units of a dual execution unit processing in order to determine if the instruction is interruptible. Additionally, backout logic is provided for saving the contents of unique registers. The backout logic uses two decodes to determine if the instruction currently executing modifies the unique registers. It is possible for a single instruction to modify more than one unique register. The backout logic of the present invention resides in both of the execution units and particularly in the unit which contains the unique register being modified by the executing instruction. If an instruction is being executed which modifies one of the unique registers, then the contents of that register are saved in a backout latch. A cancel signal is then provided if the interruptible instruction executes without causing and interrupt. However, if the interruptible instruction does cause an interrupt, then the contents of the backout latch are reloaded into the execution units.

    Blackout Logic for Dual Execution Unit Processor
    5.
    发明专利
    Blackout Logic for Dual Execution Unit Processor 未知

    公开(公告)号：CA2123448A1

    公开(公告)日：1995-03-21

    申请号：CA2123448

    申请日：1994-05-12

    Applicant: IBM

    Inventor： RAY DAVID S ,  SPENCER ALEXANDER K

    IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F15/16

    Abstract: An apparatus and method provides additional logic in both execution units 9,11 of a dual execution unit processor in order to determine if the instruction is interruptable. Additionally, backout logic 17,19 is provided for saving the contents of unique registers 13,15. The backout logic 17,19 uses two decodes to determine if the instruction currently executing modifies the unique registers 13,15. It is possible for a single instruction to modify more than one unique register 13,15. The backout logic of the present invention resides in both of the execution units 9,11 and particularly in the unit which contains the unique register being modified by the executing instruction. If an instruction is being executed which modifies one of the unique registers 13,15, then the contents of that register are saved in a backout latch 17,19. A cancel signal is then provided if the interruptable instruction executes without causing an interrupt. However, if the interruptable instruction does cause an interrupt, then the contents of the backout latch are reloaded into the execution units.

    7.
    发明专利
    未知

    公开(公告)号：BR8800248A

    公开(公告)日：1988-09-13

    申请号：BR8800248

    申请日：1988-01-25

    Applicant: IBM

    Inventor： GUPTA SATISH ,  LUMELSKY LEON ,  MASFIELD ROBERT L ,  ROMERO HECTOR G JR ,  SEGRE MARC ,  SPENCER ALEXANDER K ,  CLAIR JOE C ST ,  WAGONER JAMES DONALD

    IPC: G06F3/153 ,  G06T11/20 ,  G09G5/393 ,  G06F15/62 ,  G06F3/14

    Abstract: As the speed and capacity of graphics workstations and personal computers including graphics adapters increases, a display adapter which can be used either in such a high capacity stand alone graphics workstation or in conjunction with a large main frame host computer includes a first processor for managing adapter resources and controlling coordinate transformations; a system storage for storing instructions and data representing information to be displayed; a first-in, first-out input buffer for allowing asynchronous and overlapped communication between the graphics system and a host computer;a second processor for drawing vectors and manipulating areas to be displayed on the monitor;a frame buffer connected to the second processor for storing a bit map of data to be displayed; a colour palette connected to outputs of the frame buffer for providing appropriate colour signals to the monitor; and a hardware cursor circuit for controlling display of a cursor on the monitor.

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