公开(公告)号：JP2006285990A

公开(公告)日：2006-10-19

申请号：JP2006088892

申请日：2006-03-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DEMENT JONATHAN J ,  FEISTE KURT ALAN ,  RAY DAVID S ,  SHIPPY DAVID ,  VAN NORSTRAND ALBERT J JR

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3867

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for processing multicycle non-pipelined command sequencing. SOLUTION: In the system and the method, when a non-pipelined command is detected at an issuing point, issuing logic begins a stall in the minimum number of cycles, enough to complete the highest-speed non-pipelined command. Subsequently, an execution unit succeeds the stall until the non-pipelined command has actually been completed. Slightly before completing the command, the execution unit releases the stall to the issuing logic. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种处理多循环非流水线命令排序的系统和方法。 解决方案：在系统和方法中，当在发布点检测到非流水线命令时，发出逻辑以最小数量的循环开始停顿，足以完成最高速度的非流水线命令。 随后，执行单元成功停止，直到非流水线命令实际完成。 在完成命令之前，执行单元将释放失速到发行逻辑。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：CA2123448C

公开(公告)日：1998-10-13

申请号：CA2123448

申请日：1994-05-12

Applicant: IBM

Inventor： RAY DAVID S ,  SPENCER ALEXANDER K

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F15/16

Abstract: An apparatus and method provides additional logic in both execution units of a dual execution unit processing in order to determine if the instruction is interruptible. Additionally, backout logic is provided for saving the contents of unique registers. The backout logic uses two decodes to determine if the instruction currently executing modifies the unique registers. It is possible for a single instruction to modify more than one unique register. The backout logic of the present invention resides in both of the execution units and particularly in the unit which contains the unique register being modified by the executing instruction. If an instruction is being executed which modifies one of the unique registers, then the contents of that register are saved in a backout latch. A cancel signal is then provided if the interruptible instruction executes without causing and interrupt. However, if the interruptible instruction does cause an interrupt, then the contents of the backout latch are reloaded into the execution units.

公开(公告)号：CA1321655C

公开(公告)日：1993-08-24

申请号：CA608713

申请日：1989-08-18

Applicant: IBM

Inventor： GROHOSKI GREGORY F ,  KAHLE JAMES A ,  NGUYENPHU MYHONG ,  RAY DAVID S

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48

Abstract: AT9-88-080 TIGHTLY COUPLED MULTIPROCESSOR INSTRUCTION SYNCHRONIZATION A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：PH30201A

公开(公告)日：1997-02-05

申请号：PH39687

申请日：1989-12-13

Applicant: IBM

Inventor： GROHOSKI GREGORY F ,  KAHLE JAMES A ,  NGUYENPHU MYHONG ,  RAY DAVID S

IPC: G06F9/38 ,  G06F15/16 ,  G06F9/48 ,  G06F1/00

Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：CA2123448A1

公开(公告)日：1995-03-21

申请号：CA2123448

申请日：1994-05-12

Applicant: IBM

Inventor： RAY DAVID S ,  SPENCER ALEXANDER K

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F15/16

Abstract: An apparatus and method provides additional logic in both execution units 9,11 of a dual execution unit processor in order to determine if the instruction is interruptable. Additionally, backout logic 17,19 is provided for saving the contents of unique registers 13,15. The backout logic 17,19 uses two decodes to determine if the instruction currently executing modifies the unique registers 13,15. It is possible for a single instruction to modify more than one unique register 13,15. The backout logic of the present invention resides in both of the execution units 9,11 and particularly in the unit which contains the unique register being modified by the executing instruction. If an instruction is being executed which modifies one of the unique registers 13,15, then the contents of that register are saved in a backout latch 17,19. A cancel signal is then provided if the interruptable instruction executes without causing an interrupt. However, if the interruptable instruction does cause an interrupt, then the contents of the backout latch are reloaded into the execution units.

公开(公告)号：CA2123442A1

公开(公告)日：1995-03-21

申请号：CA2123442

申请日：1994-05-12

Applicant: IBM

Inventor： RAY DAVID S ,  THATCHER LARRY E ,  WARREN HENRY S JR

IPC: G06F9/38 ,  G06F15/16

Abstract: MULTIPLE EXECUTION UNIT DISPATCH WITH INSTRUCTION DEPENDENCY A multiple execution unit processing system is provided wherein each execution unit has an associated instruction buffer and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second unit (unit 1) the newest. Processor instructions, such as load, store, add and the like are provided to each of the instruction buffers (0,1) from an instruction cache buffer. The first instruction (oldest) is placed in buffer 0 and the next (second) instruction is stored in buffer 1. It is determined during the decode stage whether the instructions are dependent on an immediately preceding instruction. If both instructions are independent of other instructions, then they can execute in parallel. However, if the second instruction is dependent on the first, then (subsequent to the first instruction being executed) it is laterally shifted to the first instruction buffer. Instructions are also defined as being dependent on an unavailable resource. In most cases these "unavailable" instructions are allowed to executed in parallel on the execution units.