公开(公告)号：JPH10269164A

公开(公告)日：1998-10-09

申请号：JP4908998

申请日：1998-03-02

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  STEPHEN VICTOR KOSONOKKII ,  MUNETO SEIJI

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06T1/20 ,  G06T1/60 ,  G09G5/39 ,  H04N7/26 ,  H04N7/50

Abstract: PROBLEM TO BE SOLVED: To solve the problems of fractionization of the computer system and memory bandwidth by an improved method, by connecting a memory chip, which has a bus interface built in a memory chip to an existing connection point of the computer system. SOLUTION: Such a memory 63 is necessary that includes main constituent elements to sufficient density for a main memory and a frame buffer and has a bus interface(I/F) 631, an on-chip data centralized computing function 623, and an optional RAM digital-to-analog converting(DAC) function 633 integrated. For the memory 63, architectures are arranged so as to shorten a wait time and improve data bandwidth. The data centralized computing function 632 functions for motion compensation, etc., in bit block transfer, rendering, z- comparison, alpha blending, MPEG(motion picture expert group) encoding for efficient image hierarchical constitution.