CAPACITOR AND FORMING METHOD THEREOF

    公开(公告)号:JP2001223340A

    公开(公告)日:2001-08-17

    申请号:JP2001014867

    申请日:2001-01-23

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide an interconnecting level capacitor structure and a forming method thereof. SOLUTION: The capacitor structure comprises a first insulating layer disposed on an interconnecting level surface of an integrated circuit, first and second conductors which are formed in the first insulating layer and are isolated by a trench delimited by the first insulating layer, a first conductive barrier layer which is disposed on the first and second conductors and connects the first and second conductors, a second insulting layer disposed on the first conductive barrier layer, a second conductive barrier layer disposed on the second insulating layer, and a third conductor which is disposed in the trench and on the second conductive barrier layer. A capacitance is increased by using regions on a top surface, a bottom surface, and a side surface of the capacitor structure. It is possible to obtain an on-cap decoupling capacitor having a larger size without sacrificing a precious silicon space.

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