公开(公告)号：JP2005303304A

公开(公告)日：2005-10-27

申请号：JP2005112404

申请日：2005-04-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KERRY BERNSTEIN ,  EDWARD J NOWAKU ,  RAINEY BETHANN

IPC: H01L27/08 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/04 ,  H01L29/772 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/045 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a drive strength tunable FinFET, and a method of drive strength tuning the FinFET.
SOLUTION: The FinFET has either at least one perpendicular fin 125 and at least one angled fin 130 or has at least one double-gated fin and at least one split-gated fin. The drive strength of the FinFET is tuned by the total number of each type of the fin, and the angle of the angled fin 130 with the perpendicular fin 125.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供驱动强度可调谐FinFET，以及FinFET的驱动强度调谐方法。 解决方案：FinFET具有至少一个垂直翅片125和至少一个成角度的翅片130或具有至少一个双门控翅片和至少一个分裂门控翅片。 FinFET的驱动强度由每种类型的翅片的总数以及倾斜翅片130与垂直翅片125的角度来调节。版权所有：（C）2006，JPO＆NCIPI

公开(公告)号：JP2006203198A

公开(公告)日：2006-08-03

申请号：JP2006007461

申请日：2006-01-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JOSHI RAJIV V ,  WACHNIK RICHARD A ,  TAN YUE ,  KERRY BERNSTEIN

IPC: H01L27/11 ,  H01L21/8244 ,  H01L27/10

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1104

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM memory and a microprocessor, comprising a logic portion formed on a silicon substrate and an SRAM array portion. SOLUTION: The SRAM array has a body region, where at least one pair of neighboring NFETs of the SRAM cell is linked in a leakage path diffusion region 338 under shallow source/drain region 334, the leakage path diffusion region extends from the bottom of the source/drain diffusion to an embedded oxide layer 320; and at least one pair of PFETs of the neighboring SRAM cells has a body region 336, linked in a similar leakage path diffusion region under neighboring source/drain diffusion. The logic circuit portion of the microprocessor has a floating body region and an NFET, formed in a crystal orientation SOI silicon region 330 and a PFET formed in a crystal orientation bulk silicon region, and the SRAM memory portion has an NFET, formed in the crystal orientation SOI silicon region and a PFET formed in the crystal orientation silicon region. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 解决的问题：提供一种SRAM存储器和微处理器，包括形成在硅衬底上的逻辑部分和SRAM阵列部分。 解决方案：SRAM阵列具有主体区域，其中SRAM单元的至少一对相邻NFET被连接在浅源/漏区334下方的泄漏路径扩散区域338中，泄漏路径扩散区域从 源/漏扩散的底部到嵌入的氧化物层320; 并且相邻SRAM单元的至少一对PFET具有主体区域336，其连接在相邻的源极/漏极扩散部下的类似泄漏路径扩散区域中。 微处理器的逻辑电路部分具有形成在晶体取向SOI硅区域330和形成于晶体取向体硅区域中的PFET的浮体区域和NFET，并且SRAM存储器部分具有形成在晶体中的NFET 取向SOI硅区域和形成在晶体取向硅区域中的PFET。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2010232662A

公开(公告)日：2010-10-14

申请号：JP2010071719

申请日：2010-03-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KERRY BERNSTEIN ,  ELLIS-MONAGHAN JOHN JOSEPH ,  BRUCE BALCH ,  HABIB NAZMUL

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/786

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: PROBLEM TO BE SOLVED: To provide a method for normalizing strain in a semiconductor device, and a strain-normalized semiconductor device.
SOLUTION: This method includes steps of: forming first and second field-effect transistors of an integrated circuit; forming a stress layer over the first and second field-effect transistors, the stress layer inducing strain in channel regions of the first and second field-effect transistors; and selectively thinning the stress layer over at least a portion of the second field-effect transistor.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于使半导体器件中的应变归一化的方法和应变归一化半导体器件。 解决方案：该方法包括以下步骤：形成集成电路的第一和第二场效应晶体管; 在所述第一和第二场效应晶体管上形成应力层，所述应力层在所述第一和第二场效应晶体管的沟道区域中引起应变; 以及在所述第二场效应晶体管的至少一部分上选择性地稀薄所述应力层。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2003208456A

公开(公告)日：2003-07-25

申请号：JP2002365608

申请日：2002-12-17

Applicant: IBM

Inventor： KERRY BERNSTEIN ,  WATTS JOSEF S ,  WILLIAMS RICHARD Q

IPC: G06F17/50

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for a computer model for a device having a performance parameter. SOLUTION: A first bounded range and a second bounded range are included in the performance parameter. The first bounded range has performance parameter fluctuation within a single production process, and the second bounded range has performance parameter fluctuation in different device design. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2001223340A

公开(公告)日：2001-08-17

申请号：JP2001014867

申请日：2001-01-23

Applicant: IBM

Inventor： KERRY BERNSTEIN ,  NICHOLAS THEODORE SCHMIDT ,  STAMPER ANTHONY K ,  STEVEN ARTHUR SAINT ONJI ,  STEVEN HOWARD VOLDMAN

IPC: H01G4/40 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide an interconnecting level capacitor structure and a forming method thereof. SOLUTION: The capacitor structure comprises a first insulating layer disposed on an interconnecting level surface of an integrated circuit, first and second conductors which are formed in the first insulating layer and are isolated by a trench delimited by the first insulating layer, a first conductive barrier layer which is disposed on the first and second conductors and connects the first and second conductors, a second insulting layer disposed on the first conductive barrier layer, a second conductive barrier layer disposed on the second insulating layer, and a third conductor which is disposed in the trench and on the second conductive barrier layer. A capacitance is increased by using regions on a top surface, a bottom surface, and a side surface of the capacitor structure. It is possible to obtain an on-cap decoupling capacitor having a larger size without sacrificing a precious silicon space.

公开(公告)号：JP2002288253A

公开(公告)日：2002-10-04

申请号：JP2002004163

申请日：2002-01-11

Applicant: IBM

Inventor： KERRY BERNSTEIN ,  COHN JOHN M ,  NEVES JOSE L P

IPC: G06F17/50 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide a method for adding decoupling capacitance which is installed within an integrated circuit between two-dimensional design stages of the integrated circuit. SOLUTION: In the method for adding decoupling capacitance in the integrated circuit design, a step for forming a two-dimensional plan for the integrated circuit provided with relative positions of a multiple number of functional units, a step for superposing a power grid over the two-dimensional plan, a step for dividing the two dimensional plan and the power grid into a multiple number of ranges and for determining support decoupling capacitance value necessary for supporting the voltage of the power grid for each region, a step for determining a specific capacitance value, a step to determine a necessary decoupling capacitance value, based on the support decoupling capacitance value and the specific capacitance value, a step for determining a decoupling condenser region for the necessary decoupling condenser capacitance value and a step for correcting a circuit area within the region, based on the decoupling condenser region are contained.

公开(公告)号：JP2001313373A

公开(公告)日：2001-11-09

申请号：JP2001098235

申请日：2001-03-30

Applicant: IBM

Inventor： KERRY BERNSTEIN ,  GEFFKEN ROBERT M ,  STAMPER ANTHONY K ,  STEVEN A SAINT ONGE

IPC: H01L23/52 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a metal capacitor installed on a chip. SOLUTION: Capacitors (60, 126) manufactured on a semiconductor chip have strap/contacts (41A, 119A), which mutually connect bottom plates (41B, 111A) of a capacitor to a chip circuit. In one version, an extension part of a material, constituting a bottom plate of a capacitor forms a strap contact. In the other version, a capacitor (185) comprises a folded bottom plate, which uses an available space and therefore increases its capacitance, a dielectric layer and a top plate. By means of a plurality of manufacturing methods, manufacturing of these capacitors of various versions can be incorporated in a standard dual or single-damascene manufacturing process, including a copper damascene process.