公开(公告)号：US3648063A

公开(公告)日：1972-03-07

申请号：US3648063D

申请日：1970-01-28

Applicant: IBM

Inventor： HOFFMAN WILLIAM K ,  SUMILAS JOHN W

IPC: G11C19/18 ,  H01L21/00 ,  H01L27/00 ,  H01L27/07 ,  H01L27/088 ,  G11C19/00

CPC classification number: H01L27/088 ,  G11C19/18 ,  G11C19/184 ,  H01L21/00 ,  H01L27/00 ,  H01L27/0733

Abstract: A field effect transistor (FET) shift register storage circuit has a first and second FET series connected from the drain of the first FET to the source of the second FET. A storage capacitor is connected between the gate and source of the first FET. A pulse source is connected to the source of the first FET, and data stored on the capacitor is supplied to the gate of the first FET. A clocking pulse source is connected to the gate of the second FET and is adapted to provide a clocking pulse to the second FET in overlapping relationship to a pulse from the pulse source supplied through the first FET for a storage capacitor of a subsequent storage circuit. In this arrangement, both data input to the storage cell and a pulse for the storage capacitor of a subsequent storage circuit are to the first FET. This storage circuit is both very compact and of simplified structure in integrated form.

Abstract translation: 场效应晶体管（FET）移位寄存器存储电路具有从第一FET的漏极到第二FET的源极连接的第一和第二FET串联。 存储电容器连接在第一FET的栅极和源极之间。 脉冲源连接到第一FET的源极，并且存储在电容器上的数据被提供给第一FET的栅极。 时钟脉冲源连接到第二FET的栅极，并且适于以与后续存储电路的存储电容器的第一FET提供的脉冲源的脉冲重叠的关系向第二FET提供时钟脉冲。 在这种布置中，输入到存储单元的数据和后续存储电路的存储电容器的脉冲都是第一FET。 该存储电路既非常紧凑又集成形式的简化结构。

公开(公告)号：US3508218A

公开(公告)日：1970-04-21

申请号：US3508218D

申请日：1967-01-13

Applicant: IBM

Inventor： SUMILAS JOHN W

IPC: G06K17/00 ,  G11C11/06 ,  G11C5/02 ,  G11C7/00

CPC classification number: G11C11/06042 ,  G06K17/00 ,  G11C11/06035

公开(公告)号：US3344321A

公开(公告)日：1967-09-26

申请号：US47079265

申请日：1965-07-09

Applicant: IBM

Inventor： SUMILAS JOHN W

IPC: G11C11/02 ,  G05F1/12 ,  H03H9/30 ,  H03K17/04 ,  H03K17/64

CPC classification number: H03K17/04 ,  H03H9/30

公开(公告)号：US3504356A

公开(公告)日：1970-03-31

申请号：US3504356D

申请日：1967-01-13

Applicant: IBM

Inventor： PATEL ARVIND M ,  SUMILAS JOHN W

IPC: G11C11/06 ,  H03H7/32 ,  G11C7/06

CPC classification number: G11C11/06007 ,  H03H7/32

公开(公告)号：CA993994A

公开(公告)日：1976-07-27

申请号：CA148262

申请日：1972-07-31

Applicant: IBM

Inventor： SUMILAS JOHN W ,  VOGL NORBERT G JR

IPC: G06F12/16 ,  G06F11/16 ,  G11C29/00 ,  G11C29/04

Abstract: A memory storage system utilizing a plurality of storage devices, each of which contains redundancy and each of which is functionally organized on e.g. a single semiconductor chip with its own decoders. This redundancy in each device is provided by placing an extra line of cells on the chip together with a defective address store and a comparator circuit for disabling a defective line of cells and replacing it with the extra line of cells.

公开(公告)号：DE2237671A1

公开(公告)日：1973-03-01

申请号：DE2237671

申请日：1972-07-31

Applicant: IBM

Inventor： SUMILAS JOHN W ,  VOGL JUN NORBERT G

IPC: G06F12/16 ,  G06F11/16 ,  G11C29/00 ,  G11C29/04 ,  G06F11/08

Abstract: A memory storage system utilizing a plurality of storage devices, each of which contains redundancy and each of which is functionally organized on e.g. a single semiconductor chip with its own decoders. This redundancy in each device is provided by placing an extra line of cells on the chip together with a defective address store and a comparator circuit for disabling a defective line of cells and replacing it with the extra line of cells.

公开(公告)号：CA783748A

公开(公告)日：1968-04-23

申请号：CA783748D

Applicant: IBM

Inventor： SUMILAS JOHN W