公开(公告)号：DE69026928D1

公开(公告)日：1996-06-13

申请号：DE69026928

申请日：1990-11-27

Applicant: IBM

Inventor： COMBS MICHAEL LEE ,  GRUODIS ALGIRDAS JOSEPH ,  HOFFMAN DALE EUGENE ,  PUNTAR CHARLES ALBERT ,  SZABO KURT PAUL

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/319 ,  G06F11/26

Abstract: Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2 or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin. The test system also includes test pin signal receiving circuitry [26] for coupling to the test pin for receiving an electrical signal therefrom. Other predetermined ones of the control bits are coupled to the receiving circuitry for specifying, for each of the test cycles, at least one operating characteristic associated with the receiving circuitry.

公开(公告)号：DE69026928T2

公开(公告)日：1996-11-21

申请号：DE69026928

申请日：1990-11-27

Applicant: IBM

Inventor： COMBS MICHAEL LEE ,  GRUODIS ALGIRDAS JOSEPH ,  HOFFMAN DALE EUGENE ,  PUNTAR CHARLES ALBERT ,  SZABO KURT PAUL

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/319 ,  G06F11/26

Abstract: Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2 or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin. The test system also includes test pin signal receiving circuitry [26] for coupling to the test pin for receiving an electrical signal therefrom. Other predetermined ones of the control bits are coupled to the receiving circuitry for specifying, for each of the test cycles, at least one operating characteristic associated with the receiving circuitry.