公开(公告)号：DE2655575A1

公开(公告)日：1977-07-07

申请号：DE2655575

申请日：1976-12-08

Applicant: IBM

Inventor： BALYOZ JOHN ,  GRUODIS ALGIRDAS JOSEPH ,  JEN TEH-SEN ,  MIKHAIL WADIE FALTAS

IPC: H01L27/082 ,  H01L21/82 ,  H01L21/8226 ,  H01L23/528 ,  H01L27/10 ,  H01L27/118 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L27/04

Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical identical geometric form and arranged in columnar arrays.

公开(公告)号：DE69026928D1

公开(公告)日：1996-06-13

申请号：DE69026928

申请日：1990-11-27

Applicant: IBM

Inventor： COMBS MICHAEL LEE ,  GRUODIS ALGIRDAS JOSEPH ,  HOFFMAN DALE EUGENE ,  PUNTAR CHARLES ALBERT ,  SZABO KURT PAUL

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/319 ,  G06F11/26

Abstract: Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2 or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin. The test system also includes test pin signal receiving circuitry [26] for coupling to the test pin for receiving an electrical signal therefrom. Other predetermined ones of the control bits are coupled to the receiving circuitry for specifying, for each of the test cycles, at least one operating characteristic associated with the receiving circuitry.

公开(公告)号：DE1166258B

公开(公告)日：1964-03-26

申请号：DEJ0020621

申请日：1961-10-05

Applicant: IBM

Inventor： GRUODIS ALGIRDAS JOSEPH

IPC: H03K19/10

公开(公告)号：DE69026928T2

公开(公告)日：1996-11-21

申请号：DE69026928

申请日：1990-11-27

Applicant: IBM

Inventor： COMBS MICHAEL LEE ,  GRUODIS ALGIRDAS JOSEPH ,  HOFFMAN DALE EUGENE ,  PUNTAR CHARLES ALBERT ,  SZABO KURT PAUL

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/319 ,  G06F11/26

Abstract: Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2 or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin. The test system also includes test pin signal receiving circuitry [26] for coupling to the test pin for receiving an electrical signal therefrom. Other predetermined ones of the control bits are coupled to the receiving circuitry for specifying, for each of the test cycles, at least one operating characteristic associated with the receiving circuitry.

公开(公告)号：DE1275597B

公开(公告)日：1968-08-22

申请号：DEJ0025761

申请日：1964-05-02

Applicant: IBM

Inventor： GRUODIS ALGIRDAS JOSEPH

IPC: H03K19/094 ,  H03K19/21

Abstract: 1,057,917. Transistor switching circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 4, 1964 [May 7, 1963], No. 37518/66. Divided out of 1,057,916. Heading H3T. In a logic or switching circuit utilizing a transistor having an additional surface-potentialcontrolling gate electrode 24, the input is fed to the gate and a diode 60 is provided between gate and base. The circuit may exhibit an exclusive-OR function so that in the absence of inputs to the summing circuit 62, diode 60 is conductive hence the transistor 20 is cut off on the base 26. Unlike inputs to A, B reverse-bias the diode so that the transistor 20 is turned on by current in resistor 42. Like inputs at A, B, however, raise the gate 24 voltage sufficiently to cut off the transistor 20 by field effect action.