中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.025 seconds)

    SYSTEM AND METHOD FOR A MEMORY WITH COMBINED LINE AND WORD ACCESS
    1.
    发明申请
    SYSTEM AND METHOD FOR A MEMORY WITH COMBINED LINE AND WORD ACCESS 审中-公开
    具有组合线和字访问的存储器的系统和方法

    公开(公告)号：WO2006082154A2

    公开(公告)日：2006-08-10

    申请号：PCT/EP2006050433

    申请日：2006-01-25

    Applicant: IBM ,  IBM UK ,  DHONG SANG HOO ,  FLACHS BRIAN KING ,  HOFSTEE HARM PETER ,  TAKAHASHI OSAMU

    Inventor： DHONG SANG HOO ,  FLACHS BRIAN KING ,  HOFSTEE HARM PETER ,  TAKAHASHI OSAMU

    IPC: G06F13/16

    CPC classification number: G06F13/28 ,  G06F13/1626 ,  G06F13/1663

    Abstract: A system and method for a processor with memory with combined line and word access are presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

    Abstract translation: 提出了一种具有组合线和字访问的存储器的处理器的系统和方法。 系统执行窄读/写存储器访问，并使用多路复用器和锁存器对同一存储体进行宽读/写存储器访问以指导数据。 该系统使用窄读/写存储器访问处理16字节加载/请求请求，并使用宽读/写存储器访问处理128字节的DMA和指令提取请求。 在DMA请求期间，系统在一个指令周期内将16个DMA操作写入/读取存储器。 通过这样做，内存可用于在十五个其他指令周期内处理加载/存储或指令提取请求。

    METHODS AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN A DISABLED SOI CIRCUIT
    2.
    发明申请
    METHODS AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN A DISABLED SOI CIRCUIT 审中-公开
    减少SOI电路漏电流的方法和装置

    公开(公告)号：WO2006127495A3

    公开(公告)日：2007-06-07

    申请号：PCT/US2006019534

    申请日：2006-05-19

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM ,  TOSHIBA AMERICA ELECTRONIC

    Inventor： YOSHIHARA HIROSHI ,  DHONG SANG HOO ,  TAKAHASHI OSAMU ,  NAKAZATO TAKAAKI

    IPC: H03K19/00 ,  H03K17/16

    CPC classification number: H03K19/0016

    Abstract: Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially- equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on- insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node .

    Abstract translation: 方法和设备通过使至少一个开关晶体管导通来使能数字电路，使得虚拟接地节点的电压电位基本上等于用于数字电路的电源的接地节点的电压电位，其中， 使用绝缘体上硅（SOI）布置中的多个晶体管实现数字电路，并且至少一些晶体管参考虚拟接地节点; 以及通过将所述开关晶体管的栅极端子偏压到所述接地节点的电压电位以下来禁止所述数字电路。

    3.
    发明专利
    未知

    公开(公告)号：DE602006003869D1

    公开(公告)日：2009-01-08

    申请号：DE602006003869

    申请日：2006-01-25

    Applicant: IBM

    Inventor： TAKAHASHI OSAMU ,  HOFSTEE HARM PETER ,  FLACHS BRIAN KING ,  DHONG SANG HOO

    IPC: G06F13/16

    Abstract: A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

    4.
    发明专利
    未知

    公开(公告)号：AT415664T

    公开(公告)日：2008-12-15

    申请号：AT06707835

    申请日：2006-01-25

    Applicant: IBM

    Inventor： TAKAHASHI OSAMU ,  HOFSTEE HARM PETER ,  FLACHS BRIAN KING ,  DHONG SANG HOO

    IPC: G06F13/16

    Abstract: A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

    System and method for operating logic circuit
    5.
    发明专利
    System and method for operating logic circuit 审中-公开
    用于操作逻辑电路的系统和方法

    公开(公告)号：JP2005210732A

    公开(公告)日：2005-08-04

    申请号：JP2005015555

    申请日：2005-01-24

    Applicant: Internatl Business Mach Corp ,  Toshiba Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  株式会社東芝

    Inventor： MURAKAMI HIROAKI ,  QI JIEMING ,  TAKAHASHI OSAMU

    IPC: G05B19/05 ,  H03K19/00 ,  H03K19/173 ,  H03K19/20

    CPC classification number: H03K19/1737 ,  H03K19/0016

    Abstract: PROBLEM TO BE SOLVED: To provide system and method for making logic circuits operated.
    SOLUTION: The systems for making logic circuits operated include a first logic circuit 610 and a multiplexer 602. The multiplexer 602 is configured to receive a selected signal Sel_b. The selected signal Sel_b controls the multiplexer 620 so as to select one of multiplexer input signals to be provided as the output signal of the multiplexer. When the selected signal Sel_b controls the multiplexer 602 to selected one output signal of the logic circuit, the first logic circuit 610 operates in a first mode. When the selected signal Sel_b controls the multiplexer 620 so as to non-selectively control the output signal of the logic circuit, the first logic circuit 610 operates in a second mode.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供操作逻辑电路的系统和方法。 解决方案：用于使逻辑电路工作的系统包括第一逻辑电路610和多路复用器602.多路复用器602被配置为接收所选择的信号Sel_b。 所选择的信号Sel_b控制多路复用器620，以选择要被提供为多路复用器的输出信号的多路复用器输入信号之一。 当所选择的信号Sel_b控制多路复用器602以选择逻辑电路的一个输出信号时，第一逻辑电路610以第一模式工作。 当所选择的信号Sel_b控制多路复用器620以便非选择地控制逻辑电路的输出信号时，第一逻辑电路610以第二模式工作。 版权所有（C）2005，JPO＆NCIPI

    Sense amplifier having cross linked bit line structure
    8.
    发明专利
    Sense amplifier having cross linked bit line structure 有权
    具有交叉连接位线结构的感应放大器

    公开(公告)号：JP2005339778A

    公开(公告)日：2005-12-08

    申请号：JP2005152558

    申请日：2005-05-25

    Applicant: Internatl Business Mach Corp ,  Toshiba Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  株式会社東芝

    Inventor： NAKAZATO TAKAAKI ,  ASANO TORU ,  TAKAHASHI OSAMU ,  DHONG SANG

    IPC: G11C11/419 ,  H03F3/45

    CPC classification number: H03F3/45188

    Abstract: PROBLEM TO BE SOLVED: To lower the susceptibility of a sense amplifier to fluctuation of threshold voltage of a data line pulldown transistor. SOLUTION: The sense amplifier 600 includes; a pair of input bit lines 611 and 612; a pair of output data lines 621 and 622; a pair of bit line transistors 661 and 662; a pair of data line pulldown transistors 641 and 642; and a pair of first precharge circuits (635 and 636). While each of the first precharge circuits is combined with a corresponding side of intermediate nodes 631 and 632, the corresponding side of the intermediate nodes 631 and 632 is constituted to precharge the voltage on another side of the bit line 611 and 612. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：降低读出放大器对数据线下拉晶体管的阈值电压波动的敏感性。 解决方案：读出放大器600包括： 一对输入位线611和612; 一对输出数据线621,622; 一对位线晶体管661和662; 一对数据线下拉晶体管641和642; 和一对第一预充电电路（635和636）。 当每个第一预充电电路与中间节点631和632的相应侧组合时，中间节点631和632的相应侧被构造成对位线611和612的另一侧上的电压进行预充电。 版权所有（C）2006，JPO＆NCIPI

    ACCESS METHOD TO MEMORY AND MEMORY
    10.
    发明专利
    ACCESS METHOD TO MEMORY AND MEMORY 审中-公开

    公开(公告)号：JP2002073412A

    公开(公告)日：2002-03-12

    申请号：JP2001213766

    申请日：2001-07-13

    Applicant: IBM

    Inventor： DHONG SANG HOO ,  HOFSTEE HARM PETER ,  TAKAHASHI OSAMU ,  LUNTEREN JAN VAN

    IPC: G06F12/02 ,  G06F12/06

    Abstract: PROBLEM TO BE SOLVED: To disclose a method to implement an address mapping for a memory in a computer system. SOLUTION: The memory is composed of several memory banks and each memory bank identifies itself with each bank number. A block address component of a physical address is converted into a corresponding bank number and a related internal bank address. The bank number is constituted by connecting a fist lookup table output with a second lookup table output. The output of the first table is obtained by a first segment X1 and a second segment Y1 of the block address component and the output of the second table is obtained by a third segment X2 and a fourth segment Y2 of the block address component. Data saved at a specified location can be accessed by means of the bank number and the related internal bank address.

Patent Agency Ranking