公开(公告)号：JP2012124679A

公开(公告)日：2012-06-28

申请号：JP2010272970

申请日：2010-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TANAKA NOBUYASU ,  TAKEMURA KIYOSHI ,  OGAWA MAKOTO ,  OKADA TADAYUKI

IPC: H03M7/40

CPC classification number: H03M7/4031 ,  G06T9/005 ,  H03M7/30 ,  H03M7/40 ,  H03M7/46

Abstract: PROBLEM TO BE SOLVED: To reduce processing time to decode encoded data where a plurality of symbols are each replaced by a bit string.SOLUTION: Every time a bit length is input into a Huffman table decoding circuit, a counter 32 outputs a character code corresponding to the bit length as a Data In signal, a pointer table 33 outputs a number of symbols and a pointer corresponding to the bit length, and an addition circuit 34 adds them to output the result as an Insert Address signal. A shift memory circuit 31 with an insert function thus does not move character codes at addresses previous to an address by the Insert Address signal but stores the character code by the Data In signal at the address by the Insert Address signal and shifts back character codes at addresses at and subsequent to the address by the Insert Address signal.

Abstract translation: 要解决的问题：为了减少对多个符号各自被位串替换的编码数据进行解码的处理时间。 解决方案：每当将比特长度输入到霍夫曼表解码电路中时，计数器32输出与比特长度相对应的字符码作为数据输入信号，指针表33输出多个符号和相应的指针 并且加法电路34将它们作为插入地址信号输出以输出结果。 因此，具有插入功能的移位存储器电路31不会通过插入地址信号移动地址之前的地址处的字符代码，而是通过插入地址信号将该字符代码存储在地址处的数据输入信号，并将字符代码在 通过插入地址信号在地址之后的地址。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JPH07210111A

公开(公告)日：1995-08-11

申请号：JP25516494

申请日：1994-10-20

Applicant: IBM

Inventor： SUCHIIBUN PATORITSUKU TOMUSON ,  OIE MASAKI ,  OGURA AKIHIRO ,  TAKEMURA KIYOSHI ,  JIYOOZEFU DARIRU HAAUTSUDO

IPC: G09G3/20 ,  G09G5/00 ,  G09G5/36

Abstract: PURPOSE: To provide a system for enlarging a picture in the horizontal direction with a variable magnification on a high-resolution display provided with a flat panel containing a low-resolution display mode. CONSTITUTION: In a first method, an intermediate over-sampled data sequence is first obtained by over-sampling a first picture element data sequence to be enlarged at a frequency of the magnification of the frequency of the first picture element data sequence. Then a copied second data sequence which is longer than the first data sequence is obtained by linearly decimating the over-sampled data sequence with a magnification smaller than '1' and the second data sequence is displayed. In a second method, an interpolating over-sample data sequence is formed by filtrating the intermediate over-sampled data sequence and the sequence is decimated in place of the intermediate over-sample data sequence in order to further improve the quality of a screen image. Therefore, the size, complexity, and cost of the video subsystem of a computer can be reduced, because no graphic controller nor any special mechanism for display logic mechanism is required and complicated picture processing is eliminated.

公开(公告)号：JP2010258532A

公开(公告)日：2010-11-11

申请号：JP2009103213

申请日：2009-04-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TAKEMURA KIYOSHI ,  TANAKA NOBUYASU ,  OKADA TADAYUKI ,  OGAWA MAKOTO

IPC: H03M7/40

CPC classification number: H03M7/42

Abstract: PROBLEM TO BE SOLVED: To shorten the processing time of conversion from a plurality of bit lengths, allocated to a plurality of character strings, respectively, to a plurality of codes.
SOLUTION: A Huffman table decoding circuit stores a bit length bl[N] assigned to each character on input of the bit length assigned to the character, and stores the order of respective character strings among character strings to which the same bit length is assigned in code_fin[N]. Further, the number of characters to which the same bit length is assigned is stored in bl_count[M], and on the basis of the storage, a minimum code having the same bit length is stored in code_min[M]. Consequently, a selector 31 extracts the minimum code specified with bl[N] among a plurality of minimum standards stored in the code_min[N], and an adding circuit 32 performs processing for adding the minimum code to the value stored in code_fin[N] in parallel, and defines the added results as a code assigned to the character.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：将分配给多个字符串的多个位长度的转换处理时间分别缩短为多个代码。 解决方案：霍夫曼表解码电路存储在分配给字符的比特长度的输入上分配给每个字符的比特长度bl [N]，并且存储相同字符串在相同比特长度 在code_fin [N]中分配。 此外，分配相同位长的字符数存储在bl_count [M]中，并且基于存储，具有相同位长的最小代码被存储在code_min [M]中。 因此，选择器31提取存储在code_min [N]中的多个最小标准中用bl [N]指定的最小代码，并且加法电路32执行将最小代码加到存储在code_fin [N]中的值的处理， 并行，并将添加的结果定义为分配给角色的代码。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010268146A

公开(公告)日：2010-11-25

申请号：JP2009116851

申请日：2009-05-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TANAKA NOBUYASU ,  NISHINO KIYOSHI ,  TAKEMURA KIYOSHI

IPC: H03M7/40 ,  G06F17/30

CPC classification number: G11C15/00 ,  H03M7/3084

Abstract: PROBLEM TO BE SOLVED: To increase possibility that a location where data have been written lately can be selected from a plurality of locations where data are stored. SOLUTION: When a signal MATCH representing a plurality of addresses with specific character data in an associative memory cell array 26 stored therein is input, whether at least a portion of the plurality of addresses exist in a low address region is determined by a latch 90, an AND circuit 92 and an OR circuit 94; by the latch 90, a NOT circuit 96, a NAND circuit 98 and an AND circuit 100, a signal MATCH from an high address region is masked when at least a portion of the plurality of addresses exist in the low address region; and a priority encoder 102 outputs, as an address to be selected out of the plurality of addresses, the largest address out of the addresses represented by the signal MATCH inputted without being masked. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：可以从存储数据的多个位置中选择最近写入数据的位置的可能性。 解决方案：当输入表示存储在其中的相关存储单元阵列26中具有特定字符数据的多个地址的信号MATCH时，是否存在多个地址中的至少一部分存在于低地址区域中 锁存器90，AND电路92和OR电路94; 通过锁存器90，NOT电路96，NAND电路98和AND电路100，当低地址区域中存在多个地址的至少一部分时，屏蔽来自高地址区域的信号MATCH; 并且优先级编码器102作为从多个地址中选择的地址输出由不被屏蔽输入的信号MATCH所表示的地址中的最大地址。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：DE112011104620T5

公开(公告)日：2013-10-02

申请号：DE112011104620

申请日：2011-10-04

Applicant: IBM

Inventor： TANAKA NOBUYOSHI ,  OKADA TADAYUKI ,  TAKEMURA KIYOSHI ,  NISHINO KIYOSHI

IPC: H03M7/40 ,  G06F17/30 ,  G11C15/04

Abstract: Eine Verarbeitung, die unter Verwendung eines CAM durchgeführt wird, außer wenn ein Fehler in Daten auftritt, die in dem CAM gespeichert sind, kann auch dann fortgesetzt werden, wenn ein Fehler in den im CAM gespeicherten Daten auftritt. Einem Komprimierungsdatenpfad und einem Dekomprimierungsdatenpfad wird ein eingegebener Zeichencode bereitgestellt. In dem Komprimierungsdatenpfad gibt eine Schaltung 21 zum Suchen von wiederholten Daten eine Übereinstimmungsadresse einer Zeichenfolge in dem CAM und ein Zeichenfolge-Übereinstimmungssignal aus, das die Übereinstimmung der Zeichenfolge in dem CAM angibt. In dem Dekomprimierungsdatenpfad ermöglichen es die Flipflops 1001 bis 1004 dagegen, dass ein Zeichencode ohne Änderung weitergeleitet wird. Eine Auswahlvorrichtung 98 gibt die Übereinstimmungsadresse von dem Komprimierungsdatenpfad und die Anzahl von aufeinanderfolgenden Ausgaben des Zeichenfolge-Übereinstimmungssignals aus, wenn kein Paritätsfehlersignal von der Schaltung 21 zum Suchen von wiederholten Daten ausgegeben wird und die Anzahl der aufeinanderfolgenden Ausgaben des Zeichenfolge-Übereinstimmungssignals größer als oder gleich 3 ist; andernfalls gibt die Auswahlvorrichtung 98 den Zeichencode von dem Dekomprimierungsdatenpfad aus.

公开(公告)号：GB2500524A

公开(公告)日：2013-09-25

申请号：GB201310822

申请日：2011-10-04

Applicant: IBM

Inventor： TANAKA NOBUYOSHI ,  NISHINO KIYOSHI ,  OKADA TADAYUKI ,  TAKEMURA KIYOSHI

IPC: H03M7/40 ,  G06F17/30 ,  G11C15/04

Abstract: A process performed using a CAM when an error is not generated in the data stored in the CAM, can be continued even if an error is generated in the data stored in the CAM. An input character code is provided to a compressed data path and a non-compressed data path. In the compressed data path, a repeat data retrieval circuit (21) outputs a coincident address of a character string in the CAM and a character string coincident signal which indicates the coincidence of the character string in the CAM. On the other hand, in the non-compressed data path, flip-flops (1001 to 1004) send the character code without any changes. A selector (98) outputs the coincident address and the number of consecutive outputs of the character string coincident signals from the compressed data path if a parity error signal is not output from the repeat data retrieval circuit (21) and the number of consecutive outputs of the character string coincident signals is three or greater, and if not, outputs the character code from the non-compressed data path.