公开(公告)号：JPH09185593A

公开(公告)日：1997-07-15

申请号：JP33904895

申请日：1995-12-26

Applicant: IBM

Inventor： TANAKA NOBUNORI ,  OGURA AKIHIRO

IPC: G06F9/38 ,  G06F9/50 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06T15/00

Abstract: PROBLEM TO BE SOLVED: To absorb the dispersion of load by sharing a buffer for data input (FIFO) among all pipelines. SOLUTION: A dispatch processor distributes the processing of successively inputted data sets to respective parallel processors 30-1, 30-2... corresponding to their attributes or the like. A data FIFO 22 temporarily holds the substances of data successively distributed out of the dispatch processor. An enable bit 23 shows whether effective data are stored in each step of data FIFO 22 or not. A priority encoder 24 executes the storage of data sets successively outputted from the dispatch processor and the distribution of storage places (pointers) to respective pipelines by controlling the data FIFO 22 and the enable bit 23. In this case, the data FIFO 22 for inputting/outputting the data sets is shared among all the pipelines.