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公开(公告)号：DE2816711A1
公开(公告)日：1978-11-02
申请号：DE2816711
申请日：1978-04-18
Applicant: IBM
Inventor： BIRNEY RICHARD EUGENE , LEININGER JOEL CALVIN , TAYLOR GEORGE PHILLIPS
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公开(公告)号：DE2814078A1
公开(公告)日：1978-11-09
申请号：DE2814078
申请日：1978-04-01
Applicant: IBM
Inventor： LEININGER JOEL CALVIN , TAYLOR GEORGE PHILLIPS
Abstract: This carry save adder (CSA) utilizes a pair of edge-triggered flip-flops as output manifesting elements at each CSA bit position, one of these flip-flops being the "sum trigger" which registers the half-sum value (herein called the "sum bit"), and the other flip-flop of the pair being the "carry trigger" which registers the carry value resulting from the binary addition performed by the CSA at that bit position. Each trigger has a latch portion for storing a sum or carry bit value that can be set or changed only at the leading edge of a clock pulse, being stable in the period between clock pulses. A latched sum or carry output bit value at any CSA bit position can be re-entered at any time as input to the same bit position or another CSA bit position, depending upon the operation to be performed (add, left or right shift, or complement). Each trigger also produces an unlatched output sum or carry value known as a "presum" or "precarry" bit. These unlatched bit values may be utilized for trial or test purposes, such as inputs to a lookahead logic network for determining whether a proposed complemental subtraction in a division operation can or cannot be successfully performed.
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公开(公告)号：AU3392778A
公开(公告)日：1979-09-13
申请号：AU3392778
申请日：1978-03-07
Applicant: IBM
IPC: G06F13/12 , G06F7/00 , G06F9/38 , G06F13/38 , G06F15/16 , G06F15/17 , G06F15/177 , G06F3/00 , G06F9/16
Abstract: An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.
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公开(公告)号：DE2817183A1
公开(公告)日：1978-11-09
申请号：DE2817183
申请日：1978-04-20
Applicant: IBM
IPC: G06F13/12 , G06F7/00 , G06F9/38 , G06F13/38 , G06F15/16 , G06F15/17 , G06F15/177 , G06F9/18 , G06F13/06
Abstract: An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.
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