公开(公告)号：AU2474877A

公开(公告)日：1978-11-09

申请号：AU2474877

申请日：1977-05-02

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN

IPC: G06F11/00 ,  G06F12/14 ,  G06F21/24 ,  G06F13/06

公开(公告)号：AU2474377A

公开(公告)日：1978-11-09

申请号：AU2474377

申请日：1977-05-02

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  OSBORNE WILLIAM STEESE ,  GRAYBIEL LYNN ALLAN

IPC: G06F11/00 ,  G06F9/46 ,  G06F9/48 ,  G06F9/06

公开(公告)号：DE2716520A1

公开(公告)日：1977-11-10

申请号：DE2716520

申请日：1977-04-14

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  HOOD ROBERT ALLEN ,  GRAYBIEL LYNN ALLAN ,  BOCA RATON FLA ,  KAHN SAMUEL ,  OSBORNE WILLIAM STEESE ,  BOURKE DONALL GARRAID ,  PUTTLITZ FREDERIC JOHN

IPC: G06F12/02 ,  G06F9/20 ,  G06F13/06

Abstract: The look ahead circuits are for an address relocation translator which contains stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory. An additional pair of bit positions are provided with each SR to receive look ahead bits from decoder loading circuits which decode a physical address being loaded into the SR to indicate the storage unit containing the addressed block. During each subsequent address translation the loaded look ahead bits are outgated while the block address is being read from an SR. The look ahead bits are decoded for selecting the required storage unit component of the main memory, and a translator interface is switched to that unit. The look ahead bits are handled by parallel high speed circuits so that the required storage unit is selected before a storage unit cycle is generated by the translator for accessing the addressed block.

公开(公告)号：AU2474677A

公开(公告)日：1978-11-09

申请号：AU2474677

申请日：1977-05-02

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  HOOD ROBERT ALLEN ,  DAVIS MICHAEL IAN

IPC: G06F11/00 ,  G06F12/00 ,  G06F12/06 ,  G06F12/14 ,  G06F15/16 ,  G06F15/177 ,  G06F21/24 ,  G06F13/06

公开(公告)号：DE2717700A1

公开(公告)日：1977-11-10

申请号：DE2717700

申请日：1977-04-21

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  OSBORNE WILLIAM STEESE ,  GRAYBIEL LYNN ALLAN

IPC: G06F11/00 ,  G06F9/46 ,  G06F9/48 ,  G06F9/16

公开(公告)号：AU2474977A

公开(公告)日：1978-11-09

申请号：AU2474977

申请日：1977-05-02

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  HOOD ROBERT ALLEN ,  MCDERMOTT THOMAS STEPHEN ,  WISE LARRY EDWARD

IPC: G06F12/06 ,  G06F12/14 ,  G06F13/06

Abstract: System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR).

公开(公告)号：AU2474577A

公开(公告)日：1978-11-09

申请号：AU2474577

申请日：1977-05-02

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  HOOD ROBERT ALLEN ,  GRAYBIEL LYNN ALLAN ,  OSBORNE WILLIAM STEESE ,  KAHN SAMUEL

IPC: G06F12/14 ,  G06F12/02 ,  G06F13/06

公开(公告)号：DE2816711A1

公开(公告)日：1978-11-02

申请号：DE2816711

申请日：1978-04-18

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  LEININGER JOEL CALVIN ,  TAYLOR GEORGE PHILLIPS

IPC: G06F7/537 ,  G06F7/483 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527 ,  G06F7/535

公开(公告)号：DE2716051A1

公开(公告)日：1977-11-10

申请号：DE2716051

申请日：1977-04-09

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  HOOD ROBERT ALLEN

IPC: G06F11/00 ,  G06F12/00 ,  G06F12/06 ,  G06F12/14 ,  G06F15/16 ,  G06F15/177 ,  G06F21/24 ,  G06F9/18

公开(公告)号：CH619309A5

公开(公告)日：1980-09-15

申请号：CH527577

申请日：1977-04-28

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN

IPC: G06F11/00 ,  G06F12/14 ,  G06F21/24 ,  G06F13/00