公开(公告)号：JP2005197735A

公开(公告)日：2005-07-21

申请号：JP2005000213

申请日：2005-01-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KANE TERENCE L ,  MILES DARRELL L ,  SYLVESTRI JOHN D ,  TENNEY MICHAEL P

IPC: H01L21/302 ,  G01N1/32 ,  G01R31/28 ,  H01L21/30 ,  H01L21/46

CPC classification number: H01J37/32366 ,  G01N1/32 ,  G01R31/2898 ,  H01J2237/3114

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for peeling of the backside layer of a semiconductor device, thereby exposing a structure of an FEOL semiconductor of the device, in order to perform electric or physical probing (verification) or both of them later.
SOLUTION: A window is formed in a backside substrate layer of the semiconductor. Parallel ion plasma is generated, and it is guided by a shield plate for focusing so as to be brought into contact with the semiconductor only through an internal window. The focused parallel ion plasma is brought into contact with the semiconductor only through the internal window, while simultaneously rotating and tilting the semiconductor by a temperature-controlled stage to uniformly remove the semiconductor, so that a semiconductor structure is exposed at a position of the semiconductor corresponding to a backside window. The function of the backside peeling of the present invention can be strengthened by chemical reaction-aided ion beam etching (CAIBE).
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供用于剥离半导体器件的背面层的方法和系统，从而暴露设备的FEOL半导体的结构，以便执行电或物理探测（验证）或 他们两个后来。 解决方案：在半导体的背面基板层中形成窗口。 产生平行的离子等离子体，并由用于聚焦的屏蔽板引导，以便仅通过内部窗口与半导体接触。 聚焦的平行离子等离子体仅通过内部窗口与半导体接触，同时通过温度控制级同时旋转和倾斜半导体以均匀地去除半导体，使得半导体结构暴露在半导体的位置 对应于背面窗口。 通过化学反应辅助离子束蚀刻（CAIBE）可以加强本发明背面剥离的功能。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003229464A

公开(公告)日：2003-08-15

申请号：JP2002330937

申请日：2002-11-14

Applicant: IBM

Inventor： KANE TERENCE L ,  WANG YUN YU ,  CAMBRA MALCOLM P JR ,  TENNEY MICHAEL P

IPC: H01L21/66 ,  H01L23/544 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device monitor structure which can detect localized defects due to floating-body effects, particularly on SOI device wafers. SOLUTION: The semiconductor device monitor structure includes a plurality of cells containing PFET or NFET device, disposed at a perimeter of the semiconductor device monitor structure which is bordered by an insulating region such as shallow trench isolation (STI). Each cell includes polysilicon gate structure having a specific spacing given by a first distance, and a portion extending beyond the perimeter a second distance. The cells are constructed in accordance with progressively varying ground rules, so that the first distance and the second distance are non-uniform between the cells. The cells may be turned to bit file map for single-cell failures, thereby enabling detection of the localized defects due to the floating-body effects. COPYRIGHT: (C)2003,JPO