公开(公告)号：GB2571652B

公开(公告)日：2020-10-14

申请号：GB201907151

申请日：2017-10-25

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  ALBERT MANHEE CHU ,  SEONG-DONG KIM ,  TERENCE HOOK

IPC: H01L27/02 ,  G06F30/392

Abstract: A semiconductor device includes a substrate and an active area region forming a bottom source/drain region on the substrate. Vertical transistors are formed on the bottom source/drain region, where the bottom source/drain region is shared between the vertical transistors.

公开(公告)号：GB2630553B

公开(公告)日：2025-04-16

申请号：GB202414134

申请日：2023-02-20

Applicant: IBM

Inventor： TERENCE HOOK

IPC: H10D84/85 ,  H10D89/10

Abstract: A set of transistor elements includes a substrate of a first doping type and a first well and a second well, both of a second doping type and both formed on the substrate. The set of transistor elements also includes a first complementary transistor cell and a second complementary transistor cell. The set of transistor element also includes an anti-propagation region of the first doping type between the first well and the second well.

公开(公告)号：GB2630553A

公开(公告)日：2024-11-27

申请号：GB202414134

申请日：2023-02-20

Applicant: IBM

Inventor： TERENCE HOOK

IPC: H01L27/02 ,  H01L27/092

Abstract: A set of transistor elements includes a substrate of a first doping type and a first well and a second well, both of a second doping type and both formed on the substrate. The set of transistor elements also includes a first complementary transistor cell and a second complementary transistor cell. The set of transistor element also includes an anti-propagation region of the first doping type between the first well and the second well

公开(公告)号：GB2632749A

公开(公告)日：2025-02-19

申请号：GB202414147

申请日：2023-03-10

Applicant: IBM

Inventor： DAVID WOLPERT ,  LEON SIGAL ,  TERENCE HOOK

IPC: H10D89/10 ,  H10D84/85 ,  H10D84/90

Abstract: Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top- down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

公开(公告)号：GB2571652A

公开(公告)日：2019-09-04

申请号：GB201907151

申请日：2017-10-25

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  ALBERT MANHEE CHU ,  SEONG-DONG KIM ,  TERENCE HOOK

IPC: H01L27/02 ,  G06F17/50

Abstract: A method for device layout (10) with vertical transistors includes identifying active area regions (18, 28) in a layout (10) of a semiconductor device with vertical transistors. Sets of adjacent active area regions (18, 28) having a same electrical potential are determined. The sets of adjacent active area regions (18, 28) to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions (18, 28) are merged to form larger active area regions according to a priority.