公开(公告)号：GB2571652A

公开(公告)日：2019-09-04

申请号：GB201907151

申请日：2017-10-25

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  ALBERT MANHEE CHU ,  SEONG-DONG KIM ,  TERENCE HOOK

IPC: H01L27/02 ,  G06F17/50

Abstract: A method for device layout (10) with vertical transistors includes identifying active area regions (18, 28) in a layout (10) of a semiconductor device with vertical transistors. Sets of adjacent active area regions (18, 28) having a same electrical potential are determined. The sets of adjacent active area regions (18, 28) to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions (18, 28) are merged to form larger active area regions according to a priority.

公开(公告)号：GB2574952A

公开(公告)日：2019-12-25

申请号：GB201913037

申请日：2018-02-06

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  EDWARD NOWAK

IPC: H01L29/786

Abstract: A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom includes a substrate (110); a vertical fin (111) on the substrate (110), wherein the vertical fin (111) has a cross-sectional area at the base (112) of the vertical fin (111) that is larger than a cross-sectional area at the top (113) of the vertical fin (111), wherein the cross-sectional area at the top (113) of the vertical fin (111) is in the range of about 10% to about 75% of the cross-sectional area at the base (112) of the vertical fin (111); and a central gated region between the base (112) and the top (113) of the vertical fin (111).

公开(公告)号：GB2559935B

公开(公告)日：2019-08-28

申请号：GB201809710

申请日：2016-12-09

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  EDWARD NOWAK

IPC: H01L27/088 ,  H01L21/8234

Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.

公开(公告)号：GB2562442A

公开(公告)日：2018-11-14

申请号：GB201814442

申请日：2017-01-23

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  EDWARD NOWAK ,  ALBERT MANHEE CHU

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092

Abstract: Logic circuits, or logic gates, are disclosed comprising vertical transport field effect transistors and one or more active gates, wherein the number of C pp's for the logic circuit, in isolation, is equal to the number of active gates. The components of the logic circuit can be present in at least three different vertical circuit levels, including a circuit level comprising at least one horizontal plane passing through a conductive element that provides an input voltage to the one or more gate structures (7) and another conductive element that provides an output voltage of the logic circuit, and another circuit level that comprises a horizontal plane passing through a conductive bridge from the N output to P output of the field effect transistors. Such logic circuits can include single-gate inverters, two-gate inverters, NOR2 logic gates, and NAND3 logic gates, among other more complicated logic circuits.

公开(公告)号：GB2571652B

公开(公告)日：2020-10-14

申请号：GB201907151

申请日：2017-10-25

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  ALBERT MANHEE CHU ,  SEONG-DONG KIM ,  TERENCE HOOK

IPC: H01L27/02 ,  G06F30/392

Abstract: A semiconductor device includes a substrate and an active area region forming a bottom source/drain region on the substrate. Vertical transistors are formed on the bottom source/drain region, where the bottom source/drain region is shared between the vertical transistors.

公开(公告)号：GB2562442B

公开(公告)日：2019-05-01

申请号：GB201814442

申请日：2017-01-23

Applicant: IBM

Inventor： BRENT ALAN ANDERSON ,  EDWARD NOWAK ,  ALBERT MANHEE CHU

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092

Abstract: Logic circuits, or logic gates, are disclosed comprising vertical transport field effect transistors and one or more active gates, wherein the number of CPP's for the logic circuit, in isolation, is equal to the number of active gates. The components of the logic circuit can be present in at least three different vertical circuit levels, including a circuit level comprising at least one horizontal plane passing through a conductive element that provides an input voltage to the one or more gate structures and another conductive element that provides an output voltage of the logic circuit, and another circuit level that comprises a horizontal plane passing through a conductive bridge from the N output to P output of the field effect transistors. Such logic circuits can include single-gate inverters, two-gate inverters, NOR2 logic gates, and NAND3 logic gates, among other more complicated logic circuits.