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公开(公告)号：DE68923864D1
公开(公告)日：1995-09-21
申请号：DE68923864
申请日：1989-04-19
Applicant: IBM
Inventor： CLARA JEAN-LOUIS , JACHIMCZYK PHILIPPE , LE PENNEC JEAN-FRANCOIS , MASSIERA LOUIS , THERIAS PHILIPPE
Abstract: Memory and peripheral chip select apparatus for allowing the addressing of different memory and peripheral elements by a processor (410). The different memory and peripheral elements include a first memory elements and first peripheral elements (150, 181) located into a first adapter pluggable into a base machine (4) and second memory elements and second peripheral elements (250, 281) located into a second adapter pluggable into the base machine (4). The processor 410 further addresses third memory elements and third peripheral elements (420, 430, 440, 450) located into the base machine (4). The first and second memory elements include code which have a determined type and a determined level of release. The invention is characterized in the fact that it further includes means (410) for reading the type and the level of the release of said code included into one of said first and second adapter and means (420) responsive to said reading and operating when said codes of both of said first and second adapters are of the same type for selecting that of said first or second memory means which has the code of higher level of release when said processor (410) desires to access the code of a given type into one of said adapters.
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Patent Agency Ranking
公开(公告)号：DE69124743D1
公开(公告)日：1997-03-27
申请号：DE69124743
申请日：1991-11-29
Applicant: IBM
Inventor： BARDET GERARD , LE PENNEC JEAN-FRANCOIS , MICHEL PATRICK , THERIAS PHILIPPE
Abstract: A store and forward mechanism for telecommunication equipments including means (300) for deserializing a HDLC frame of data which is received from a first telecommunication node into a sequence of n-bits words. The frame includes a header, a data field and a frame checking sequence (FCS) generated by said first telecommunication node. The apparatus further includes processing means for generating n-bit words corresponding to a new header of said received HDLC frame. The store and forward apparatus comprises serializing means (600) receiving said processed n-bits words from said storage for generating a new HDLC frame comprising said new header field and a corresponding new FCS which is to be transmitted to said second telecommunication node. The apparatus further includes means (500) receiving the received HDLC frame simultaneously to the deserializing means and which computes a first partial FCS covering the data field only of the HDLC frame, and means (200) for storing that partial FCS. During the forward phase, the n-bits words which are to be transmitted to the next telecommunication node are simultaneously received by the HDLC serializer and by means (800) for computing a second partial FCS covering said data field only. At the end of the serialization process of the data field of the HDLC frame, the two partial results are compared in order to detect the occurence of an error which might have appeared in the storage during the computing of the new header of the frame. The result of that comparison is used as a control signal for altering the value of the FCS computed by the HDLC serializer before it is transmitted to the telecommunication line field of the HDLC frame, the two partial results are compared in order to detect the occurence of an error which might have appeared in the storage during the computing of the new header of the frame. The result of that comparison is used as a control signal for altering the value of the FCS computed by the HDLC serializer before it is transmitted to the telecommunication line. Since the computing of both the first and second partial FCS is respectively performed during the deserializing of the HDLC frame and the serializing of the processed n-bit data words, no extra delay is required. The integrity of data during its storage in RAM is therefore provided without needed additional processing resources since the processor which is included within the store and forward mechanism has its resources which remain fully allocated for the store and forward process.
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公开(公告)号：DE69124743T2
公开(公告)日：1997-08-14
申请号：DE69124743
申请日：1991-11-29
Applicant: IBM
Inventor： BARDET GERARD , LE PENNEC JEAN-FRANCOIS , MICHEL PATRICK , THERIAS PHILIPPE
Abstract: A store and forward mechanism for telecommunication equipments including means (300) for deserializing a HDLC frame of data which is received from a first telecommunication node into a sequence of n-bits words. The frame includes a header, a data field and a frame checking sequence (FCS) generated by said first telecommunication node. The apparatus further includes processing means for generating n-bit words corresponding to a new header of said received HDLC frame. The store and forward apparatus comprises serializing means (600) receiving said processed n-bits words from said storage for generating a new HDLC frame comprising said new header field and a corresponding new FCS which is to be transmitted to said second telecommunication node. The apparatus further includes means (500) receiving the received HDLC frame simultaneously to the deserializing means and which computes a first partial FCS covering the data field only of the HDLC frame, and means (200) for storing that partial FCS. During the forward phase, the n-bits words which are to be transmitted to the next telecommunication node are simultaneously received by the HDLC serializer and by means (800) for computing a second partial FCS covering said data field only. At the end of the serialization process of the data field of the HDLC frame, the two partial results are compared in order to detect the occurence of an error which might have appeared in the storage during the computing of the new header of the frame. The result of that comparison is used as a control signal for altering the value of the FCS computed by the HDLC serializer before it is transmitted to the telecommunication line field of the HDLC frame, the two partial results are compared in order to detect the occurence of an error which might have appeared in the storage during the computing of the new header of the frame. The result of that comparison is used as a control signal for altering the value of the FCS computed by the HDLC serializer before it is transmitted to the telecommunication line. Since the computing of both the first and second partial FCS is respectively performed during the deserializing of the HDLC frame and the serializing of the processed n-bit data words, no extra delay is required. The integrity of data during its storage in RAM is therefore provided without needed additional processing resources since the processor which is included within the store and forward mechanism has its resources which remain fully allocated for the store and forward process.
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公开(公告)号：DE68923864T2
公开(公告)日：1996-05-02
申请号：DE68923864
申请日：1989-04-19
Applicant: IBM
Inventor： CLARA JEAN-LOUIS , JACHIMCZYK PHILIPPE , LE PENNEC JEAN-FRANCOIS , MASSIERA LOUIS , THERIAS PHILIPPE
Abstract: Memory and peripheral chip select apparatus for allowing the addressing of different memory and peripheral elements by a processor (410). The different memory and peripheral elements include a first memory elements and first peripheral elements (150, 181) located into a first adapter pluggable into a base machine (4) and second memory elements and second peripheral elements (250, 281) located into a second adapter pluggable into the base machine (4). The processor 410 further addresses third memory elements and third peripheral elements (420, 430, 440, 450) located into the base machine (4). The first and second memory elements include code which have a determined type and a determined level of release. The invention is characterized in the fact that it further includes means (410) for reading the type and the level of the release of said code included into one of said first and second adapter and means (420) responsive to said reading and operating when said codes of both of said first and second adapters are of the same type for selecting that of said first or second memory means which has the code of higher level of release when said processor (410) desires to access the code of a given type into one of said adapters.
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公开(公告)号：DE68914831T2
公开(公告)日：1994-11-17
申请号：DE68914831
申请日：1989-06-29
Applicant: IBM
Inventor： THERIAS PHILIPPE , DALMAS PHILIPPE , MICHEL PATRICK , LE PENNEC JEAN-FRANCOIS , ESTEBAN DANIEL
Abstract: A Terminal adapter for a telecommunication network having a receiver (400) for multiple HDLC communication channels. The receiver includes a BCC calculator (460) for computing and checking the validity of a received HDLC CNM frame. The terminal adapter further includes means (340, 350, 360) for detecting the reception of a specific CNM header included into a CNM frame on anyone of said HDLC communication channels and means (394, 530/X) responsive to said detection for setting the BCC calculator (460) to a predefined state. The latter state corresponds to the state of the BCC calculator (460) after a computation of BCC for the specific CNM header. Therefore the BCC calculator (460) can proceeds with computation of said BCC for said CNM frame.
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公开(公告)号：DE68914831D1
公开(公告)日：1994-05-26
申请号：DE68914831
申请日：1989-06-29
Applicant: IBM
Inventor： THERIAS PHILIPPE , DALMAS PHILIPPE , MICHEL PATRICK , LE PENNEC JEAN-FRANCOIS , ESTEBAN DANIEL
Abstract: A Terminal adapter for a telecommunication network having a receiver (400) for multiple HDLC communication channels. The receiver includes a BCC calculator (460) for computing and checking the validity of a received HDLC CNM frame. The terminal adapter further includes means (340, 350, 360) for detecting the reception of a specific CNM header included into a CNM frame on anyone of said HDLC communication channels and means (394, 530/X) responsive to said detection for setting the BCC calculator (460) to a predefined state. The latter state corresponds to the state of the BCC calculator (460) after a computation of BCC for the specific CNM header. Therefore the BCC calculator (460) can proceeds with computation of said BCC for said CNM frame.
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