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公开(公告)号：JPH10320279A
公开(公告)日：1998-12-04
申请号：JP9792298
申请日：1998-04-09
Applicant: IBM
Inventor： RAVI KUMAR ARIMIRI , DODSON JOHN STEVEN , JERRY DON LEWIS , TIMOTHY M SCKELGAN
Abstract: PROBLEM TO BE SOLVED: To accelerate read access while efficiently using all usable cache lines by processing the position of a parity error through a parity error control(PEC) unit when that error occurs. SOLUTION: When the parity error is first detected from a parity checker 84, a PEC unit 98 forcedly turns a cache into busy mode. In the busy mode, a request is either retried or not confirmed until the error is processed. The PEC unit 98 reads an address tag (and a status bit) from the designated block of the next other directory (where no error occurs) and directly supplies this address tag to the concerned directory, concretely, a correspondent comparator 82. After the concerned array is updated, the cache can restart ordinary operation through the PEC unit 98.
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公开(公告)号：JPH10320280A
公开(公告)日：1998-12-04
申请号：JP9793698
申请日：1998-04-09
Applicant: IBM
Inventor： RAVI KUMAR ARIMIRI , DODSON JOHN STEVEN , JERRY DON LEWIS , TIMOTHY M SCKELGAN
Abstract: PROBLEM TO BE SOLVED: To speed up read access while efficiently using all usable cache lines without using any excessive logic circuit for a critical bus by using two directories for a cache. SOLUTION: A line shown as 'CPU snoop' generally indicates the operation of cache from a mutual connecting part on the side of CPU and can include direct mutual connection to the CPU or direct mutual connection to another snoop device, namely, a high-order level cache. When writing a memory block in a cache memory, it is necessary to write an address tag (and other bits such as a state field and an inclusion field) in both directories 72 and 96. Write can be executed while using write queues 94 more than one connected to the directories 72 and 96. Therefore, the latitude to execute snoop operation is increased.
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