公开(公告)号：EP2102907A4

公开(公告)日：2013-12-04

申请号：EP07855216

申请日：2007-12-18

Applicant: IBM

Inventor： FRIED DAVID MICHAEL ,  HERGENROTHER JOHN MICHAEL ,  MCNAB SHAREE JANE ,  ROOKS MICHAEL J ,  TOPOL ANNA

IPC: H01L23/544 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/20 ,  G03F9/00 ,  H01J37/317 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84

CPC classification number: G03F9/708 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/7088 ,  H01J37/3174 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2008082942A3

公开(公告)日：2008-09-25

申请号：PCT/US2007087835

申请日：2007-12-18

Applicant: IBM ,  FRIED DAVID MICHAEL ,  HERGENROTHER JOHN MICHAEL ,  MCNAB SHAREE JANE ,  ROOKS MICHAEL J ,  TOPOL ANNA

Inventor： FRIED DAVID MICHAEL ,  HERGENROTHER JOHN MICHAEL ,  MCNAB SHAREE JANE ,  ROOKS MICHAEL J ,  TOPOL ANNA

IPC: H01L23/544

CPC classification number: G03F9/708 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/7088 ,  H01J37/3174 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

Abstract translation: 一种用于将集成电路芯片的制造水平的第一组特征与包括形成在衬底中的高原子量层的电子束对准目标对准并且使用电子束光刻形成第一组特征并且用于对准第二组特征 将集成电路芯片的相同制造水平的一组特征集合到在衬底中形成的光学对准目标并使用光刻形成第二组特征，光学对准目标本身与电子束对准目标对准。 还有一种形成电子束对准目标的结构的方法。

公开(公告)号：WO2007112361A3

公开(公告)日：2008-04-10

申请号：PCT/US2007064946

申请日：2007-03-26

Applicant: IBM ,  CABRAL CYRIL JR ,  DELIGIANNI HARIKLIA ,  KNARR RANDOLPH F ,  MALHOTRA SANDRA G ,  ROSSNAGEL STEPHEN ,  SHAO XIAOYAN ,  TOPOL ANNA ,  VEREECKEN PHILIPPE M

Inventor： CABRAL CYRIL JR ,  DELIGIANNI HARIKLIA ,  KNARR RANDOLPH F ,  MALHOTRA SANDRA G ,  ROSSNAGEL STEPHEN ,  SHAO XIAOYAN ,  TOPOL ANNA ,  VEREECKEN PHILIPPE M

IPC: H01L29/02

CPC classification number: H01L23/485 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a suicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the suicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

Abstract translation: 一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的自杀或锗化物层，例如钴和/或镍; 接触层包括位于介电层顶部并且在空腔内并且与底部上的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。 金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。 当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。 当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。